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參數(shù)資料
| 型號： | IBM13Q4739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊（4M x 72高速存儲器陣列結構）) |
| 中文描述： | 4米× 72注冊內(nèi)存模塊（帶寄存同步動態(tài)內(nèi)存模塊（4米× 72高速存儲器陣列結構）） |
| 文件頁數(shù)： | 1/56頁 |
| 文件大?。?/td> | 1471K |
| 代理商： | IBM13Q4739CC |
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IBM13Q4739CC
4M x 72 Registered SDRAM Module
08J0512.E24526
Released 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 56
IBM0316409C 4M x 412/10, 3.3V, SR. IBM0316169C 1M x 1612/8, 3.3V, SR. IBM0316809C 2M x 812/9, 3.3V, SR.
Features
200-Pin JEDEC Standard, Buffered 8- Byte Dual
In-line Memory Module
4M x 72 Synchronous DRAM DIMM
Performance:
CAS Latency = 2*
f
CK
Clock Frequency
t
CK2
Clock Cycle
t
AC2
Clock Access Time
* SDRAM CAS latency = 2; DIMM CAS Latency = 3
Inputs and outputs are LVTTL (3.3V) compatible
Single 3.3V to 3.6V Power Supply
Single Pulsed RAS interface
Fully Synchronous to positive Clock Edge
Data Mask control
Auto Refresh (CBR) and Self Refresh
Automatic and controlled Precharge Commands
Programmable Operation:
-SDRAM CAS Latency: 2
-Burst Type: Sequential or Interleave
-Burst Length: 2
-Operation: Burst Read and Write or Multiple
Burst Read with Single Write
Suspend Mode and Power Down Mode
11/10/1 Addressing (Row/Column/Bank)
4096 Refresh cycles distributed across 64ms
Parallel Presence Detect
Card size: 6.05" x 1.50" x 0.169"
Gold contacts
SDRAM
S
in TSOP Type II Package
Description
IBM13Q4739CC is a buffered 200-pin Synchronous
DRAM Dual In-line Memory Module (DIMM) which is
organized as a 4Mx72 high-speed memory array.
The DIMM uses eighteen x4 SDRAMs in 400mil
TSOP II packages. The DIMM achieves high speed
data transfer rates of up to 66MHz by employing a
prefetch/pipeline hybrid architecture that supports
the JEDEC 1N rule while allowing very low burst
power.
The DIMM is intended to comply with all non-
optional JEDEC standards set for the 200-pin buff-
ered SDRAM DIMMs.
All control and address signals are synchronized
with the positive edge of an externally supplied
clock. They are latched in an on-DIMM pipeline reg-
ister and presented to the SDRAMs on the following
clock.
Prior to any Access operation, the CAS latency,
burst type, burst length, and burst operation type
must be programmed into the DIMM by address
inputs A0-A11 using the Mode Register Set cycle.
The DIMM uses parallel presence detects imple-
mented according to the JEDEC standard.
All IBM 200-pin DIMMs provide a high performance,
flexible 8-byte interface in a 6.05” long high-perfor-
mance footprint. Related products include both EDO
DRAM and SDRAM unbuffered DIMMs in both non-
parity x64 and ECC-Optimized x72 configurations in
the 168 pin form factor.
-10
66
15
11.3
Units
MHz
ns
ns
Card Outline
1
101
16
116
17
117
(Front)
(Back)
78
178
79
179
100
200
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