參數(shù)資料
型號: IBM13Q4739CC
廠商: IBM Microeletronics
英文描述: 4M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊(4M x 72高速存儲器陣列結(jié)構(gòu)))
中文描述: 4米× 72注冊內(nèi)存模塊(帶寄存同步動態(tài)內(nèi)存模塊(4米× 72高速存儲器陣列結(jié)構(gòu)))
文件頁數(shù): 10/56頁
文件大?。?/td> 1471K
代理商: IBM13Q4739CC
IBM13Q4739CC
4M x 72 Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 56
08J0512.E24526
Released 4/98
Burst Read Command
The Burst Read command is initiated by having S0 and CAS low while holding RAS and WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register
sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page). The delay from the start
of the command to when the data from the first cell appears on the outputs is equal to the value of the CAS
latency that is set in the Mode Register.
Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read command, with the only
restriction being that the interval that separates the commands must be at least one clock cycle. When the
previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst
length. The data from the first Read command continues to appear on the outputs until the CAS latency from
the interrupting Read command is satisfied, at this point the data from the interrupting Read command
appears.
Burst Read Operation
(Burst Length = 2, CAS Latency = 2)
Read Interrupted by a Read Timing
(Burst Length = 2, CAS Latency = 2)
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t
CK2,
DQs
CAS latency = 2
NOP
CK0
T0
T2
T1
T3
T4
T5
T6
T7
T8
DOUT A0
DOUT A1
NOTE: Data is delayed one cycle due to on-DIMM pipeline register.
COMMAND
READ A
READ B
NOP
NOP
NOP
t
CK2,
DQs
CAS latency = 2
NOP
CK0
T0
T2
T1
T3
T4
T5
DOUT B0
DOUT B1
DOUT A0
NOTE: Data is delayed one cycle due to on-DIMM pipeline register
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