參數(shù)資料
型號(hào)： IBM13Q4739CC
廠商： IBM Microeletronics
英文描述： 4M x 72 Registered SDRAM Module(帶寄存同步動(dòng)態(tài)RAM模塊（4M x 72高速存儲(chǔ)器陣列結(jié)構(gòu)）)
中文描述： 4米× 72注冊(cè)內(nèi)存模塊（帶寄存同步動(dòng)態(tài)內(nèi)存模塊（4米× 72高速存儲(chǔ)器陣列結(jié)構(gòu)））
文件頁(yè)數(shù)： 11/56頁(yè)
文件大?。?/td> 1471K
代理商： IBM13Q4739CC
IBM13Q4739CC
4M x 72 Registered SDRAM Module
08J0512.E24526
Released 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 56
Read Interrupted by a Write
To interrupt a burst read with a Write command, DQM must be used to avoid data contention on the I/O bus
by placing the DQs (output drivers) in a high impedance state at least one clock cycle before the Write com-
mand is initiated. To insure the DQs are tri-stated one cycle before the Write operation begins, DQM must be
activated at least 3 clock cycles before the Write command and be deactivated in the same clock cycle as the
Write command.
When the CAS latency is 2, the minimum interval between the Read and Write commands is one clock cycle.
Minimum Read to Write Interva
(Burst Length = 2, CAS Latency = 2)
Non-Minimum Read to Write Interval
(Burst Length = 2, CAS Latency = 2)
COMMAND
NOP
BANK A
ACTIVATE
NOP
READ A
WRITE A
NOP
NOP
DQM
: “H” or “L”
NOTE: Data is delayed one cycle due to on-DIMM pipeline register
DIN A0
DIN A1
Must be Hi-Z during
Write Command
t
CK2,
DQs
CAS latency = 2
CK0
T0
T2
T1
T3
T4
T5
T6
T7
NOP
1 Clk Interval
COMMAND
NOP
READ A
NOP
NOP
NOP
WRITE B
NOP
NOP
NOP
DQM
: “H” or “L”
NOTE: Data is delayed one cycle due to on-DIMM pipeline register
DIN B0
DIN B1
DIN B2
DIN
Must be Hi-Z during
the Write Command
t
CK2,
DQs
CAS latency = 2
CK0
T0
T2
T1
T3
T4
T5
T6
T7
T8
DOUT A0
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