參數(shù)資料
型號(hào)： IBM13Q4739CC
廠商： IBM Microeletronics
英文描述： 4M x 72 Registered SDRAM Module(帶寄存同步動(dòng)態(tài)RAM模塊（4M x 72高速存儲(chǔ)器陣列結(jié)構(gòu)）)
中文描述： 4米× 72注冊(cè)內(nèi)存模塊（帶寄存同步動(dòng)態(tài)內(nèi)存模塊（4米× 72高速存儲(chǔ)器陣列結(jié)構(gòu)））
文件頁(yè)數(shù)： 15/56頁(yè)
文件大?。?/td> 1471K
代理商： IBM13Q4739CC
IBM13Q4739CC
4M x 72 Registered SDRAM Module
08J0512.E24526
Released 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 56
Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-
charge command or the auto-precharge function. When a Read or a Write command is given to the DIMM,
the CAS timing accepts one extra address, column address A10/AP, to allow the active bank to automatically
begin precharge at the earliest possible moment during the Burst Read or Write cycle. If A10/AP is low when
the READ or WRITE command is issued, then normal Read or Write Burst operation is executed and the
bank remains active at the completion of the burst sequence. If A10/AP is high when the Read or Write com-
mand is issued, then the auto-precharge function is engaged. During autoprecharge, a Read command will
execute as normal with the exception that the active bank will begin to precharge before all Burst Read cycles
have been completed. This feature allows the Precharge operation to be partially or completely hidden during
the Burst Read cycles (dependent upon burst length) thus improving system performance for random data
access. Auto-precharge can also be implemented during Write commands although precharge can not begin
any sooner than is possible by issuing the Precharge command directly to the device.
A Read or Write command without auto-precharge can be terminated in the midst of a Burst operation. How-
ever, a Read or Write command with auto-precharge can not be interrupted before the entire Burst operation
is completed. Therefore use of a Read, Write, Precharge, or Burst Stop command is prohibited during a Read
or Write cycle with auto-precharge.
If A10/AP is high when a Read command is issued, the Read with Auto-Precharge function is initiated. The
SDRAM automatically enters the Precharge operation two clocks after the Read command is registered for
CAS latencies of 2. Once the Precharge operation has started the bank cannot be reactivated until the Pre-
charge time (t
RP
) has been satisfied. It should be noted that the device will not respond to the Auto-Precharge
command if the device is programmed for full page Burst Read or Write cycles, or full page Burst Read cycles
with single Write operation.
If A10/AP is high when a Write command is issued, the Write with Auto-Precharge function is initiated. The
SDRAM automatically enters the Precharge operation one clock delay from the last Burst Write cycle. This
delay is referred to as t
DPL
. The bank undergoing auto-precharge can not be reactivated until t
DPL
and t
RP
are
satisfied. This is referred to as t
DAL,
Data-in to Active delay (t
DAL
= t
DPL
+ t
RP
).
Burst Read with Auto-Precharge
(Burst Length = 2, CAS Latency = 2)
COMMAND
NOP
NOP
NOP
NOP
Auto-Precharge
CK0
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
BANK A
ACTIVE
NOP
NOP
t
RP
t
CK2,
DQs
CAS latency = 2
Begin Autoprecharge
Bank can be reactivated at completion of tRP
DOUT A0
DOUT A1
NOTE: Data is delayed one cycle due to on-DIMM pipeline register
*
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