參數(shù)資料
型號: IBM13Q4739CC
廠商: IBM Microeletronics
英文描述: 4M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊(4M x 72高速存儲器陣列結(jié)構(gòu)))
中文描述: 4米× 72注冊內(nèi)存模塊(帶寄存同步動態(tài)內(nèi)存模塊(4米× 72高速存儲器陣列結(jié)構(gòu)))
文件頁數(shù): 17/56頁
文件大?。?/td> 1471K
代理商: IBM13Q4739CC
IBM13Q4739CC
4M x 72 Registered SDRAM Module
08J0512.E24526
Released 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 17 of 56
When the Refresh cycle has completed, both SDRAM banks will be in the precharged (idle) state. A delay
between the Auto Refresh command (CBR) and the next Activate command or subsequent Auto Refresh
command must be greater than or equal to the RAS cycle time (t
RC
).
Self Refresh Command
The SDRAMs on the DIMM have built-in timers to accommodate Self Refresh operation. The Self Refresh
command is defined by having S0, RAS, CAS and CKE0 held low with WE high at the rising edge of the
clock. Once the command is registered, CKE0 must be held low to keep the device in Self Refresh mode.
When the SDRAMs enter Self Refresh mode all of the external control signals, except CKE0, are masked
after a clock cycle delay. The clock is internally disabled during Self Refresh operation to save power. The
user may halt the external clock while the device is in Self Refresh mode, however, the clock must be
restarted before the device can exit Self Refresh operation. Once the clock is cycling, the SDRAMs will exit
Self Refresh operation on the third positive clock transition after CKE0 is returned high. A minimum delay
time is required when the device exits Self Refresh operation and before the next command can be issued.
This delay is equal to the RAS cycle time t
RC
which is 5 clocks for this DIMM.
Data Mask
The SDRAM DIMM has a Data Mask function that can be used in conjunction with data Read and Write
cycles. When the Data Mask is activated (DQM high) during a Write cycle, the Write operation is prohibited
on the next cycle. If the Data Mask is activated during a Read cycle, the data outputs are disabled and
become high impedance after a three clock delay, independent of CAS latency.
No Operation Command
The No Operation command should be used in cases when the SDRAMs are in a idle or a wait state. The
purpose of the No Operation command is to prevent the SDRAMs from registering any unwanted commands
between operations. A No Operation command is registered when S0 is low with RAS, CAS, and WE held
high at the rising edge of the clock. A No Operation command will not terminate a previous operation that is
still executing, such as a Burst Read or Write cycle.
Deselect Command
The Deselect command performs the same function as a No Operation command. Deselect command occurs
when S0 is brought high, the RAS, CAS, and WE signals become don’t cares.
Power Down Mode
In order to reduce standby power consumption, a power down mode is available. All banks must be pre-
charged and the necessary Precharge delay (t
RP
) must occur before the SDRAMs can enter the Power Down
mode. Once the Power Down mode is initiated by holding CKE0 low, all of the receiver circuits except CK0
and CKE0 are gated off. The Power Down mode does not perform any Refresh operations, therefore the
device can’t remain in Power Down mode longer than the Refresh period (t
REF
) of the device.
The Power Down mode is exited by bringing CKE0 high. A two-clock delay after the registration of CKE0 high
is required for the SDRAMs to exit the Power Down mode.
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