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參數(shù)資料
| 型號： | IBM13Q4739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊（4M x 72高速存儲器陣列結(jié)構(gòu)）) |
| 中文描述： | 4米× 72注冊內(nèi)存模塊（帶寄存同步動態(tài)內(nèi)存模塊（4米× 72高速存儲器陣列結(jié)構(gòu)）） |
| 文件頁數(shù)： | 20/56頁 |
| 文件大?。?/td> | 1471K |
| 代理商： | IBM13Q4739CC |
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IBM13Q4739CC
4M x 72 Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 20 of 56
08J0512.E24526
Released 4/98
Clock Enable (CKE0) Truth Table
Current State
CKE0
Command
Action
Notes
Previous
Cycle
Current
Cycle
S0
RAS
CAS
WE
A11/BS A10 - A0
Self Refresh
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
Exit Self Refresh with Device Deselect
2
L
H
L
H
H
H
X
X
Exit Self Refresh with No Operation
2
L
H
L
H
H
L
X
X
ILLEGAL
2
L
H
L
H
L
X
X
X
ILLEGAL
2
L
H
L
L
X
X
X
X
ILLEGAL
2
L
L
X
X
X
X
X
X
Maintain Self Refresh
Power Down
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
Power Down mode exit, all banks idle
2
L
H
L
X
X
X
X
X
ILLEGAL
2
L
L
X
X
X
X
X
X
Maintain Power Down Mode
All Banks Idle
H
H
H
X
X
X
Refer to the Idle State section of the
Current State Truth Table
3
H
H
L
H
X
X
3
H
H
L
L
H
X
3
H
H
L
L
L
H
X
X
CBR Refresh
H
H
L
L
L
L
OP Code
Mode Register Set
4
H
L
H
X
X
X
Refer to the Idle State section of the
Current State Truth Table
3
H
L
L
H
X
X
3
H
L
L
L
H
X
3
H
L
L
L
L
H
X
X
Entry Self Refresh
4
H
L
L
L
L
L
OP Code
Mode Register Set
L
X
X
X
X
X
X
X
Power Down
4
Any State
other than
listed above
H
H
X
X
X
X
X
X
Refer to operations in the Current
State Truth Table
H
L
X
X
X
X
X
X
Begin Clock Suspend next cycle
5
L
H
X
X
X
X
X
X
Exit Clock Suspend next cycle
L
L
X
X
X
X
X
X
Maintain Clock Suspend
1. For the given Current State CKE0 must be low in the previous cycle.
2. When CKE0 has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for
CKE0 (t
CKS
) must be satisfied before any command other than Exit is issued.
3. The address inputs (A11 - A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table
for more information.
4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
5. Must be a legal command as defined in the Current State Truth Table.
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