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參數資料
| 型號： | IBM13Q4739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊（4M x 72高速存儲器陣列結構）) |
| 中文描述： | 4米× 72注冊內存模塊（帶寄存同步動態(tài)內存模塊（4米× 72高速存儲器陣列結構）） |
| 文件頁數： | 21/56頁 |
| 文件大?。?/td> | 1471K |
| 代理商： | IBM13Q4739CC |
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IBM13Q4739CC
4M x 72 Registered SDRAM Module
08J0512.E24526
Released 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 21 of 56
Current State Truth Table
(
CKE0 is assumed to be active (high) in the previous cycle for all entries. The Current State is
the state of the bank that the command is being applied to.
)
Current
State
Command
Action
Notes
S0
RAS CAS WE
A11/BS
A10/AP - A0
Description
Idle
L
L
L
L
OP Code
Mode Register Set
Set the Mode Register
1
L
L
L
H
X
X
Auto or Self Refresh Start Auto or Self Refresh
1, 2
L
L
H
L
X
X
Precharge
No Operation
L
L
H
H
BS
Row Address Bank Activate
Activate the specified bank and row
L
H
L
L
BS
Column
Write w/o Precharge ILLEGAL
3
L
H
L
H
BS
Column
Read w/o Precharge ILLEGAL
3
L
H
H
L
X
X
Burst Termination
No Operation
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation or Power Down
4
Row Active
L
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
X
X
Precharge
Precharge
5
L
L
H
H
BS
Row Address Bank Activate
ILLEGAL
3
L
H
L
L
BS
Column
Write
Start Write; Determine if Auto Precharge
6, 7
L
H
L
H
BS
Column
Read
Start Read; Determine if Auto Precharge
6, 7
L
H
H
L
X
X
Burst Termination
No Operation
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation
Read
L
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
X
X
Precharge
Terminate Burst; Start the Precharge
L
L
H
H
BS
Row Address Bank Activate
ILLEGAL
3
L
H
L
L
BS
Column
Write
Terminate Burst; Start the Write cycle
7, 8
L
H
L
H
BS
Column
Read
Terminate Burst; Start a new Read cycle
7, 8
L
H
H
L
X
X
Burst Termination
Terminate the Burst
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
1. Both Banks must be idle otherwise it is an illegal action.
2. If CKE0 is active (high) the SDRAM DIMM starts the Auto (CBR) Refresh operation, if CKE0 is inactive (low) than the Self Refresh
mode is entered.
3. The Current State refers only refers to one of the banks, if BS selects this bank then the action is illegal. If BS selects the bank not
being referenced by the Current State then the action may be legal depending on the state of that bank.
4. If CKE0 is inactive (low) than the Power Down mode is entered, otherwise there is a No Operation.
5. The minimum and maximum Active time (t
RAS
) must be satisfied.
6. The RAS to CAS Delay (t
RCD
) must occur before the command is given.
7. Column address A10 is used to determine if the Auto Precharge function is activated.
8. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
9. The command is illegal if the minimum bank to bank delay time (t
RRD
) is not satisfied.
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