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參數(shù)資料
| 型號(hào)： | IBM13Q4739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 72 Registered SDRAM Module(帶寄存同步動(dòng)態(tài)RAM模塊（4M x 72高速存儲(chǔ)器陣列結(jié)構(gòu)）) |
| 中文描述： | 4米× 72注冊(cè)內(nèi)存模塊（帶寄存同步動(dòng)態(tài)內(nèi)存模塊（4米× 72高速存儲(chǔ)器陣列結(jié)構(gòu)）） |
| 文件頁數(shù)： | 26/56頁 |
| 文件大?。?/td> | 1471K |
| 代理商： | IBM13Q4739CC |
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IBM13Q4739CC
4M x 72 Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 26 of 56
08J0512.E24526
Released 4/98
Output Characteristics
(T
A
= 0 to +70C, V
DD
= 3.3V to 3.6V)
Symbol
Parameter
Min.
Max.
Units
I
I(L)
Input Leakage Current, any input
(0.0V
≤
V
IN
≤
3.6V), All Other Pins Not Under Test = 0V
-10
+10
μ
A
I
O(L)
Output Leakage Current (DQ)
(D
OUT
is disabled, 0.0V
≤
V
OUT
≤
3.6V)
-1
+1
μ
A
V
OH
Output Level (TTL)
Output “H” Level Voltage (I
OUT
= -2.0mA)
2.4
V
DD
V
V
OL
Output Level (TTL)
Output “L” Level Voltage (I
OUT
= +2.0mA)
0.0
0.4
V
I
O(L)
Output Leakage Current (PD1 - PD8)
-10
+10
μ
A
Standby and Refresh Currents
(T
A
= 0 to +70C, V
DD
= 3.3V to 3.6V)
Parameter
Symbol
Test Condition
Organization
Units
Notes
x72
Precharge Standby Current in Power
Down Mode
I
CC1
P
CKE0
≤
V
IL
(max), t
CK
= 15ns
186
mA
I
CC1
PS
CKE0
≤
V
IL
(max), t
CK
= Infinity
38
mA
Precharge Standby Current in Non-
Power Down Mode
I
CC1
N
CKE0
≥
V
IH
(min), t
CK
= 15ns,
S0
≥
V
IH
(min)
Input Change every 30ns
604
mA
I
CC1
NS
CKE0
≥
V
IH
(min), t
CK
= Infinity
No Input Change
182
mA
Active Standby Current in Power Down
Mode
I
CC2
P
CKE0
≤
V
IL
(max), t
CK
= 15ns
186
mA
1
I
CC2
PS
CKE0
≤
V
IL
(max), t
CK
= Infinity
38
mA
1
Active Standby Current in Non-Power
Down Mode
I
CC2
N
CKE0
≥
V
IH
(min), t
CK
= 15ns,
S0
≥
V
IH
(min)
Input Change every 30ns
604
mA
I
CC2
NS
CKE0
≥
V
IH
(min), t
CK
= Infinity
No Input Change
272
mA
Auto (CBR) Refresh Current
I
CC3
CAS Latency = 2
t
RC
≥
t
RC
(min)
1774
mA
2, 3, 4
Self Refresh Current
I
CC4
CKE0
≤
0.2V
167
mA
1. Active Standby Current will be higher if Clock Suspend is entered during a Burst Read cycle (1mA per DQ).
2. The specified values are valid when addresses are changed no more than once during t
CK
(min).
3. The specified values are valid when No Operation commands are registered on every rising clock edge during t
RC
(min).
4. The specified values are valid when data inputs (DQs) are stable during t
RC
(min).
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