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| 型號： | IBM13Q4739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊（4M x 72高速存儲器陣列結(jié)構(gòu)）) |
| 中文描述： | 4米× 72注冊內(nèi)存模塊（帶寄存同步動態(tài)內(nèi)存模塊（4米× 72高速存儲器陣列結(jié)構(gòu)）） |
| 文件頁數(shù)： | 27/56頁 |
| 文件大小： | 1471K |
| 代理商： | IBM13Q4739CC |
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IBM13Q4739CC
4M x 72 Registered SDRAM Module
08J0512.E24526
Released 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 27 of 56
AC Characteristics
(TA= 0 to +70C, VDD= 3.3V to 3.6V)
1. An initial pause of 100
μ
s is required after power-up, then a Precharge All Banks command must be given followed by a minimum of
two Auto (CBR) Refresh cycles before the Mode Register Set operation can begin.
2. AC timing tests have V
IL
= 0.8V and V
IH
= 2.0V with the timing referenced to the 1.40V crossover point.
3. The Transition time is measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
4. AC measurements assume t
T
=1ns.
5. In addition to meeting the transition rate specification, the clock and CKE0 must transit between V
IH
and V
IL
(or between V
IL
and
V
IH
) in a monotonic manner.
Operating Currents
(T
A
= 0 to +70C, V
DD
= 3.3V to 3.6V)
Symbol
Parameter
Test Condition
CAS
Latency
t
RC
(min)
Organization
Units
Notes
x72
I
CC6
Operating Current
Burst Length = 2
t
RC
=
t
RC
(min)
t
CK
≥
t
CK
(min)
I
O
= 0mA
CL=2
105 ns
1954
mA
1, 2, 3
1. The specified values are obtained with the output open.
2. The specified values are valid when addresses and DQs are changed no more than once during t
CK
(min).
3. The specified values are obtained when the programmed burst length is executed to completion without interruption by a subse-
quent burst Read or Write cycle.
Output
Input
Clock
t
OH
t
SETUP
t
HOLD
t
AC
t
LZ
1.4V
0.8V
1.4V
1.4V
2.0V
t
T
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