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參數(shù)資料
| 型號(hào)： | IBM13Q4739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 72 Registered SDRAM Module(帶寄存同步動(dòng)態(tài)RAM模塊（4M x 72高速存儲(chǔ)器陣列結(jié)構(gòu)）) |
| 中文描述： | 4米× 72注冊(cè)內(nèi)存模塊（帶寄存同步動(dòng)態(tài)內(nèi)存模塊（4米× 72高速存儲(chǔ)器陣列結(jié)構(gòu)）） |
| 文件頁數(shù)： | 29/56頁 |
| 文件大?。?/td> | 1471K |
| 代理商： | IBM13Q4739CC |
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IBM13Q4739CC
4M x 72 Registered SDRAM Module
08J0512.E24526
Released 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 29 of 56
Refresh Cycle
Symbol
Parameter
Value
Units
Notes
Min.
Max.
t
REF
Refresh Period
—
64
ms
1, 2
t
SREX
Self Refresh Exit Time
3CK0 + ONE
t
RC
—
ns
3
1. 4096 cycles.
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-
up” the device.
3. Self Refresh Exit is an asynchronous operation. Self Refresh Exit is accomplished by starting the clock (CK0) and then asserting
CKE0 high. During the exit time (t
SREX
), no commands may be issued until t
RC
is satisfied and CKE0 must remain high. It is recom-
mended to hold S0 high during the self refresh exit time, but NOP commands may be issued with each rising clock edge during this
period as an alternative.
Read Cycle
Symbol
Parameter
Value
Units
Notes
Min.
Max.
t
OH
Data Out Hold Time
3.3
—
ns
t
LZ
Data Out to Low Impedance Time
3.3
—
ns
t
HZ2
Data Out to High Impedance Time
3.3
10.8
ns
1
t
DQZ
DQM Data Out Disable Latency
3
—
CK0
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
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