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參數(shù)資料
| 型號： | IBM13Q8734HCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 Registered SDRAM Module(8M x 72 200腳寄存同步動態(tài)RAM模塊) |
| 中文描述： | 8米× 72注冊內(nèi)存模塊（8米× 72 200腳寄存同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 243K |
| 代理商： | IBM13Q8734HCA |
IBM13Q8734HCA
8M x 72 Registered SDRAM Module
04K8916.C75645C
4/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 14
Input/Output Functional Description
Symbol
Type
Signal
Polarity
Positive
Edge
Function
CK0
Input
Pulse
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
CKE0
Input
Level
Active
High
Activates the CK0 signal when high and deactivates the CK0 signal when low. By deactivating
the clock, CKE0 low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
S0
Input
Pulse
Active
Low
S0 enables the command decoder when low and disables the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations
continue.
RAS,CAS
WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation
to be executed by the SDRAM.
A12/BS1
A13/BS0
Input
Level
—
Select which SDRAM bank is to be active (Bank 0 - Bank3).
A0 - A9,
A11
A10/AP
A12/BS1
A13/BS0
Input
Level
—
During a Bank Activate command cycle, A0-A10/AP and A11 defines the row address (RA0-
RA11) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8) when
sampled at the rising clock edge. In addition to the column address, A10/AP is used to invoke
Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high, auto-
precharge is selected and BS0, BS1 define the bank to be precharged. If A10/AP is low, auto-
precharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BS0, BS1 to control
which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the
state of BS. If A10/AP is low, then BS0, BS1 is used to define which bank to precharge.
DQ0 -
DQ71
Input
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAM DIMMs.
DQM
Input
Pulse
Mask
Active
High
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled
high. In Read mode, DQM has a latency of three clock cycles and controls the output buffers
like an output enable. In Write mode, DQM has a latency of one and operates as a word mask
by allowing input data to be written if it is low but blocks the Write operation if DQM is high.
V
DD
, V
SS
Supply
Power and ground for the input buffers and the core logic.
Presence Detect
Pin
Value
Notes
PD1
1
1
PD2
1
1
PD3
0
1
PD4
1
1
PD5
1
1
PD6
0
1
PD7
1
1
PD8
1
1
ID1
1
2
ID2
0
2
ID3
0
2
1. 0 = driven to V
, 1 = open
2. 0 = ground, 1 = open
Discontinued (4/1/00 - last order; 7/31/00 - last ship)
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