參數(shù)資料
型號: IBM13Q8734HCA
廠商: IBM Microeletronics
英文描述: 8M x 72 Registered SDRAM Module(8M x 72 200腳寄存同步動態(tài)RAM模塊)
中文描述: 8米× 72注冊內(nèi)存模塊(8米× 72 200腳寄存同步動態(tài)內(nèi)存模塊)
文件頁數(shù): 9/14頁
文件大?。?/td> 243K
代理商: IBM13Q8734HCA
IBM13Q8734HCA
8M x 72 Registered SDRAM Module
04K8916.C75645C
4/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 14
Mode Register Set Cycle
Symbol
Parameter
Value
Units
Notes
Min.
Max.
t
RSC
Mode Register Set Cycle Time
20
ns
1
1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Read Cycle
Symbol
Parameter
Value
Units
Notes
Min.
Max.
t
OH
Data Out Hold Time
3.3
ns
t
LZ
Data Out to Low Impedance Time
0.3
ns
t
HZ2
Data Out to High Impedance Time
3.3
10.8
ns
1
t
DQZ
DQM Data Out Disable Latency
3
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Refresh Cycle
Symbol
Parameter
Value
Units
Notes
Min.
Max.
t
REF
Refresh Period
64
ms
1, 2
t
SREX
Self Refresh Exit Time
10
ns
3
1. 4096 cycles.
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-
up” the device.
3. Self Refresh Exit is an asynchronous operation. Self Refresh Exit is accomplished by starting the clock (CK0) and then asserting
CKE0 high. During the exit time (t
SREX
), no commands may be issued until t
RC
is satisfied and CKE0 must remain high. It is rec-
ommended to hold S0 high during the self refresh exit time, but NOP commands may be issued with each rising clock edge during
this period as an alternative.
Write Cycle
Symbol
Parameter
Value
Units
Min.
Max.
t
DS
Data In Setup Time
3.3
ns
t
DH
Data In Hold Time
2.3
ns
t
DPL2
Data input to Precharge
1
CLK
t
DQW
DQM Write Mask Latency
1
CLK
Discontinued (4/1/00 - last order; 7/31/00 - last ship)
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