- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379205 > IBM13Q8739CC (IBM Microeletronics) 8M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊（8M x 72高速存儲器陣列結(jié)構(gòu)）) PDF資料下載
參數(shù)資料
| 型號： | IBM13Q8739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊（8M x 72高速存儲器陣列結(jié)構(gòu)）) |
| 中文描述： | 8米× 72注冊內(nèi)存模塊（帶寄存同步動態(tài)內(nèi)存模塊（8米× 72高速存儲器陣列結(jié)構(gòu)）） |
| 文件頁數(shù)： | 12/56頁 |
| 文件大?。?/td> | 903K |
| 代理商： | IBM13Q8739CC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
IBM13Q8739CC
8M x 72 Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 56
08J0513.E24526
Revised 4/98
Burst Write Command
The Burst Write command is initiated by having S0/S1 on one deck, CAS and WE low while holding RAS high
at the rising edge of the clock. The address inputs determine the starting column address. Due to the on-
board register, there is one CAS latency required for Burst Write cycles. Data for the first Burst Write cycle
must be applied on the DQ pins on the clock cycle after the Write command is issued. The remaining data
inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the
burst has finished, any additional data supplied to the DQ pins will be ignored.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write command, with the only
restriction being that the interval that separates the commands must be at least one clock cycle. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data will be
written into the device until the programmed burst length is satisfied.
Burst Write Operation
(Burst Length = 2, CAS latency = 2)
Write Interrupted by a Write
(Burst Length = 2, CAS latency = 2)
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
DQs
DIN A0
DIN A1
NOP
CK0
T0
T2
T1
T3
T4
T5
T6
T7
T8
Extra data is masked.
don’t care
Note: Data is delayed one cycle due to on-DIMM pipeline register
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
DQs
DIN A0
DIN B0
DIN B1
NOP
CK0
T0
T2
T1
T3
T4
T5
T6
T7
T8
Note: Data is delayed one cycle due to on-DIMM pipeline register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM13T16644NPA | 16M x 64 PC100 SDRAM(1MB PC100 同步動態(tài)RAM) |
| IBM13T2649JC | 2M x 64 SDRAM SO DIMM(Small Outline Dual In-Line Memory Module)(2M x 64 小外形雙列直插同步動態(tài)RAM模塊) |
| IBM13T2649NC | 2M x 64 SDRAM SO DIMM(2M x 64小外形雙列直插同步動態(tài)RAM模塊) |
| IBM13T4644MC | 1M x 64 SDRAM SO DIMM(1M x 64 同步動態(tài)RAM模塊) |
| IBM13T1649NC | 1M x 64 SDRAM SO DIMM(1M x 64 同步動態(tài)RAM模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM14H5481 | 制造商:AVED Memory Products 功能描述: |
| IBM14H5540 | 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述: |
| IBM17R8251 | 制造商:AVED Memory Products 功能描述: |
| IBM17R8252 | 制造商:AVED Memory Products 功能描述: |
| IBM1805T | 制造商:Schneider Electric 功能描述:IBM1805T |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。