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參數(shù)資料
| 型號： | IBM13Q8739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊（8M x 72高速存儲器陣列結構）) |
| 中文描述： | 8米× 72注冊內存模塊（帶寄存同步動態(tài)內存模塊（8米× 72高速存儲器陣列結構）） |
| 文件頁數(shù)： | 18/56頁 |
| 文件大?。?/td> | 903K |
| 代理商： | IBM13Q8739CC |
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IBM13Q8739CC
8M x 72 Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 18 of 56
08J0513.E24526
Revised 4/98
Clock Suspend Mode
During normal access mode, CKE0 held high enables the clock. When CKE0 is registered low, while at least
one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the inter-
nal clock and suspends or “freezes” any clocked operation that was currently being executed. There is a two-
clock delay between the registration of CKE0 low and the time at which the SDRAMs’ operation suspends.
While in Clock Suspend mode, the SDRAMs ignore any new commands that are issued. The Clock Suspend
mode is exited by bringing CKE0 high. There is a two-clock cycle delay from when CKE0 returns high to when
Clock Suspend mode is exited.
When the operation of the SDRAMs is suspended during the execution of a Burst Read operation, the last
valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited.
If Clock Suspend mode is initiated during a Burst Write operation, the input data is masked and ignored until
the Clock Suspend mode is exited.
Clock Suspend During a Read Cycle
(Burst Length = 2, CAS latency = 2)
Clock Suspend During a Write Cycle
(Burst Length = 2, CAS latency = 2)
CK0
T0
T2
T1
T3
T4
T5
T6
T7
T8
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
CKE0
DQs
DOUT A0
DOUT A1
: “H” or “L”
A two-clock delay before
Suspend operation starts
A two-clock delay to exit
the Suspend command
DOUT element at the DQs when the
Suspend operation starts is held valid
Note: Data is delayed one cycle due to on-DIMM pipeline register
CK0
T0
T2
T1
T3
T4
T5
T6
T7
T8
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
CKE0
DQs
: “H” or “L”
A two-clock delay before
Suspend operation starts
A two-clock delay to exit
the Suspend command
DIN is masked during the Clock Suspend Period
DIN A1
DIN A0
Note: Data is delayed one cycle due to on-DIMM pipeline register
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