參數(shù)資料
型號(hào)： IBM13Q8739CC
廠商： IBM Microeletronics
英文描述： 8M x 72 Registered SDRAM Module(帶寄存同步動(dòng)態(tài)RAM模塊（8M x 72高速存儲(chǔ)器陣列結(jié)構(gòu)）)
中文描述： 8米× 72注冊(cè)內(nèi)存模塊（帶寄存同步動(dòng)態(tài)內(nèi)存模塊（8米× 72高速存儲(chǔ)器陣列結(jié)構(gòu)））
文件頁(yè)數(shù)： 9/56頁(yè)
文件大?。?/td> 903K
代理商： IBM13Q8739CC
IBM13Q8739CC
8M x 72 Registered SDRAM Module
08J0513.E24526
Revised 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 56
Read and Write Access Modes
A Read or Write cycle can occur after bank activation. This is accomplished by setting RAS high and CAS low
at the clock’s rising edge after the necessary RAS-to-CAS delay (t
RCD
). WE must also be defined at this time
to determine whether the Access cycle is a Read operation (WE high) or a Write operation (WE low).
The SDRAM DIMM provides a wide variety of fast-access modes. A single Read or Write command will ini-
tiate a serial Read or Write operation on successive clock cycles at 66MHz data rates. The number of serial
data bits for each access is equal to the burst length, programmed into the Mode Register. Although the burst
length is user programmable, the boundary of the Burst cycle is restricted to specific segments of the page
length.
For example, the 4M x 4 SDRAM device used on this module has a page length of 1024 bits (defined by CA0-
CA9). For a burst length of 2 programmed into the Mode Register, 512 boundary segments (2 bits each) are
addressable. The first access begins at the column address supplied to the device during the READ or Write
command (CA0-CA9). However, the second access is not necessarily the next higher order column address.
The second access is a function of the starting address, the burst sequence, and burst boundary. Restated,
the burst sequence is contained to two bits associated with one of the 512 possible boundary segments. The
actual boundary segment (1 of 512) is determined by the nine higher order column addresses (CA1-CA9).
The first access within this boundary segment is determined by the low order column address (CA0) and the
following access is determined by the burst sequence.
The above discussion does not apply when full page burst is programmed into the Mode Register. Full page
burst length works only with the sequential burst sequence and has no address boundaries. The SDRAM
device will continue bursting data even after the entire page burst length has been satisfied. The burst
sequence will start at the column address defined during the Read or Write cycle and will increment sequen-
tially until the highest order column address has been reached. At this point, the burst counter will reset to
address 0 and continue to perform burst read or Burst Write operations sequentially until either a Burst Stop
command is issued, a Precharge command is issued to the bursting bank, or until a new Read or Write com-
mand is issued which will interrupt the existing burst and begin a new burst at the new starting column
address.
Similar to Page Mode of conventional DRAMs, a Read or Write cycle cannot begin until the sense amplifiers
latch the selected row address information. The refresh period (t
REF
) is what limits the number of random col-
umn accesses to an activated bank. A new burst access can be done even before the previous burst ends.
The ability to interrupt a Burst operation at every clock cycle is supported; this is referred to as the 1N rule.
When the previous burst is interrupted by another Read or Write command, the remaining addresses are
overridden by the new address once the CAS Latency has been satisfied.
Precharging an active bank after each Read or Write operation is not necessary providing the same row is to
be accessed again. To perform a Read or Write cycle to a different row within an activated bank, the bank
must be precharged and a new Bank Activate command must be issued. When both Bank A and Bank B are
activated, interleaved (ping pong) bank Read or Write operations are possible. Using the programmed burst
length and alternating the access and Precharge operations between the two banks can provide fast and
seamless data Access operation among many different pages. When the two banks are activated, Column to
Column interleave operation can be done between two different pages. Finally, Read or Write commands can
be issued to the same bank or between active banks on every clock cycle.
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