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參數(shù)資料
| 型號(hào)： | IBM13T1649NC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 1M x 64 SDRAM SO DIMM(1M x 64 同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 100萬蘇× 64 SDRAM的內(nèi)存（100萬× 64同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 1/15頁(yè) |
| 文件大?。?/td> | 291K |
| 代理商： | IBM13T1649NC |
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IBM13T4644MC
IBM13T1649NC
1M x 64 SDRAM SO DIMM
75H5936
GA14-4477-03
Rev 3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 15
Features
144 Pin (emerging) JEDEC Standard, 8 Byte
Small Outline Dual-In-line Memory Module
1Mx64 Synchronous DRAM SO DIMM
Performance:
All inputs and outputs are LVTTL (3.3V) compat-
ible
Single 3.3V
±
0.3V Power Supply
Single Pulsed RAS interface
SDRAMs have 2 internal banks
Fully Synchronous to positive Clock Edge
Programmable Operation:
- CAS Latency: 1, 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8, Full-Page (Full-
Page supports Sequential burst only)
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
Data Mask for Byte Read/Write control
Auto Refresh (CBR) and Self Refresh
Automatic and controlled Precharge Commands
Suspend Mode and Power Down Mode
11/8/1 Addressing (Row/Column/Bank)
4096 refresh cycles distributed across 64ms
Serial Presence Detect
Card size: 2.66" x 1.0" x 0.149"
Au contacts
SDRAMS in TSOP Type II Package
Description
IBM13T1649NC is a 144-pin Synchronous DRAM
Small Outline Dual In-line Memory Module (SO
DIMM) which is organized as a 1Mx64 high-speed
memory array. The SO DIMM uses 4 1Mx16
SDRAMs in 400mil TSOP II packages. The SO
DIMM achieves high speed data transfer rates of up
to 100MHz by employing a prefetch/pipeline hybrid
architecture that supports the JEDEC 1N rule while
allowing very low burst power.
The SO DIMM is intended to comply with all JEDEC
standards set for 144 pin SDRAM SO DIMMs.
All control, address, and data input/output circuits
are synchronized with the positive edge of the exter-
nally supplied clock inputs.
All inputs are sampled at the positive edge of each
externally supplied clock (CK0, CK1). Internal oper-
ating modes are defined by combinations of the
RAS, CAS, WE, S0, DQMB, and CKE0 signals. A
command decoder initiates the necessary timings
for each operation. A 12 bit address bus accepts
address information in a row/column multiplexing
arrangement.
Prior to any access operation, the CAS latency,
burst type, burst length, and burst operation type
must be programmed into the SO DIMM by address
inputs A0-A9 during the mode register set cycle.
The SO DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two pin IIC
protocol. The first 128 bytes of serial PD data are
used by the DIMM manufacturer. The last 128 bytes
are available to the customer.
All IBM 144-pin SO DIMMs provide a high perfor-
mance, flexible 8-byte interface in a 2.66" long
space-saving footprint. Related products are in the
EDO DRAM SO DIMM family.
-10
3
100
10
8
Units
CAS Latency
Clock Frequency
Clock Cycle
Clock Access Time
f
CK
t
CK
t
AC
MHz
ns
ns
Card Outline
1
2
143
144
(Front)
(Back)
59
60
61
62
IBM11M4730C4M x 72 E12/10, 5.0V, Au.
Discontinued (12/98 - last order; 9/99 last ship)
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