參數(shù)資料
型號(hào)： IBM13T2649JC
廠商： IBM Microeletronics
英文描述： 2M x 64 SDRAM SO DIMM(Small Outline Dual In-Line Memory Module)(2M x 64 小外形雙列直插同步動(dòng)態(tài)RAM模塊)
中文描述： 200萬(wàn)蘇× 64 SDRAM的內(nèi)存（小外形雙列內(nèi)存模組）（2米× 64小外形雙列直插同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 11/15頁(yè)
文件大?。?/td> 299K
代理商： IBM13T2649JC
IBM13T2649JC
2M x 64 SDRAM SO DIMM
75H5376
GA14-4476-02
Rev 3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 15
+-
Common Parameters
Symbol
Parameter
-10
Units
Min.
Max.
t
CS
Command Setup Time
3
—
ns
t
CH
Command Hold Time
1
—
ns
t
AS
Address and Bank Select Set-up Time
3
—
ns
t
AH
Address and Bank Select Hold Time
1
—
ns
t
RCD
RAS to CAS Delay
30
—
ns
t
RC
Bank Cycle Time
90
120000
ns
t
RAS
Active Command Period
60
120000
ns
t
RP
Precharge Time
30
—
ns
t
RRD
Bank to Bank Delay Time
20
—
ns
t
CCD
CAS to CAS Delay Time (Same Bank)
1
—
CLK
Refresh Cycle
Symbol
Parameter
-10
Units
Notes
Min.
Max.
t
SREX
Self Refresh Exit Time
10ns +
t
RC
—
ns
3
t
REF
Refresh Period
—
64
ms
1, 2
1. 4096 cycles.
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-
up” the device.
3. Self Refresh Exit is an asynchronous operation. Self refresh exit is accomplished by starting the clock (CLK) and then asserting
CKE high. During the exit time (tSREX), no commands may be issued until t
RC
is satisfied and CKE must remain high. It is recom-
mended to hold CS high during the self refresh exit time, but NOP commands may be issued with each rising clock edge during
this period as an alternative. To prevent erroneous exit of self refresh operation, a glitch suppressor circuit is incorporated into the
CKE receiver. If CKE is asserted high (system noise) for less than 10ns (approximately), then the device will not exit self refresh
operation.
Read Cycle
Symbol
Parameter
-10
Units
Notes
Min.
Max.
t
OH
Data Out Hold Time
3
—
ns
t
LZ
Data Out to Low Impedance Time
3
—
ns
t
HZ3
Data Out to High Impedance Time, CL= 3
3
8
ns
1
t
HZ2
Data Out to High Impedance Time, CL= 2
3
10
ns
1
t
HZ1
Data Out to High Impedance Time, CL= 1
3
18
ns
1
t
DQZ
DQM Data Out Disable Latency
2
—
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Discontinued (12/98 - last order; 9/99 last ship)
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