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參數資料
| 型號： | IBM13T4644MC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 1M x 64 SDRAM SO DIMM(1M x 64 同步動態(tài)RAM模塊) |
| 中文描述： | 100萬蘇× 64 SDRAM的內存（100萬× 64同步動態(tài)內存模塊） |
| 文件頁數： | 5/15頁 |
| 文件大?。?/td> | 291K |
| 代理商： | IBM13T4644MC |
IBM13T4644MC
IBM13T1649NC
1M x 64 SDRAM SO DIMM
75H5936
GA14-4477-03
Rev 3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 15
Serial Presence Detect (Part 1 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
80
08
04
0B
08
01
4000
01
A0
Notes
0
Number of Serial PD Bytes Written during Production
128
1
Total Number of Bytes in Serial PD device
256
2
Fundamental Memory Type
SDRAM
3
Number of Row Addresses on Assembly
11
4
Number of Column Addresses on Assembly
8
5
Number of DIMM Banks
1
6 - 7
Data Width of Assembly
x64
8
Voltage Interface Level of this Assembly
LVTTL
9
SDRAM Device Cycle Time
-10
10.0ns
10
SDRAM Device Access Time from Clock at
CL=3
-10
8.0ns
80
11
DIMM Configuration Type
Non-Parity
00
80
10
00
01
8F
02
07
01
01
00
12
Refresh Rate/Type
SR/1X(15.625us)
13
Primary SDRAM Device Width
x16
14
Error Checking SDRAM Device Width
N/A
15
SDRAM Device Attr: Min Clk Delay, Random Col Access
1 Clock
16
SDRAM Device Attributes: Burst Lengths Supported
1,2,4,8, Full Page
17
SDRAM Device Attributes: Number of Device Banks
2
18
SDRAM Device Attributes: CAS Latencies Supported
1, 2, 3
19
SDRAM Device Attributes: CS Latency
0
20
SDRAM Device Attributes: WE Latency
0
21
SDRAM Module Attributes
Unbuffered
22
SDRAM Device Attributes: General
Wr-1/Rd Burst, Precharge All,
Auto-Precharge, V
DD
0E
23
Minimum Clock Cycle at CL2=2
-10
15.0ns
F0
24
Maximum Data Access Time (t
AC
) from
Clock at CLX-1
-10
9.0ns
90
25
Minimum Clock Cycle Time at CL=1
-10
30.0ns
78
26
Maximum Data Access Time (t
AC
) from
Clock at CLX-2
-10
27.0ns
6C
27
Minimum Row Precharge Time (t
RP
)
-10
30ns
1E
28
Minimum Row Active to Row Active delay
(t
RRD
)
-10
20ns
14
29
Minimum RAS to CAS delay (t
RCD
)
-10
30ns
1E
2D
02
30
Minimum RAS Pulse width (t
RAS
)
-10
45ns
31
Module Bank Density
8MB
32 - 61
Reserved
Undefined
00
62
SPD Revision
01
01
63
Checksum for bytes 0 - 62
Checksum Data
cc
1
64 - 71
Manufacturers’ JEDEC ID Code
IBM
A400000000000000
72
Module Manufacturing Location
Toronto, Canada
91
Vimercate, Italy
53
1. cc = Checksum Data byte, 00-FF (Hex)
2. “R” = Alphanumeric revision code, A-Z, 0-9
3. rr = ASCII coded revision code byte “R”
4. yy = Binary coded decimal year code, 00-99 (Decimal)
00-63 (Hex)
5. ww = Binary coded decimal week code, 01-52 (Decimal)
01-34 (Hex)
6. ss = Serial number data byte, 00-FF (Hex)
Discontinued (12/98 - last order; 9/99 last ship)
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