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參數(shù)資料
| 型號(hào)： | IBM13T4644MC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 1M x 64 SDRAM SO DIMM(1M x 64 同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 100萬蘇× 64 SDRAM的內(nèi)存（100萬× 64同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 291K |
| 代理商： | IBM13T4644MC |
IBM13T4644MC
IBM13T1649NC
1M x 64 SDRAM SO DIMM
75H5936
GA14-4477-03
Rev 3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 15
AC Characteristics
(T
A
= 0 to +70C, V
DD
= 3.3V
±
0.3V)
1. An initial pause of 100
μ
s is required after power-up, then a Precharge All Banks command must be given followed by a minimum of
two Auto (CBR) Refresh cycles before the Mode Register Set operation can begin.
2. AC timing tests have V
IL
= 0.8V and V
IH
= 2.0V with the timing referenced to the 1.40V crossover point.
Operating Currents
(T
A
= 0 to +70C, V
DD
= 3.3V
±
0.3V)
Symbol
Parameter
Test Condition
CAS
Latency
CL=1
CL=2
CL=3
CL=1
CL=2
CL=3
CL=1
CL=2
CL=3
CL=1
CL=2
CL=3
t
RC
(min)
Speed
Sort
-10
-10
-10
-10
-10
-10
-10
-10
-10
-10
-10
-10
Organization
x64
380
440
520
320
420
520
280
400
520
260
400
540
Units
Notes
I
DD5
Operating Current
Burst Length = 1
t
RC
=
t
RC
(min)
t
CK
≥
t
CK
(min)
I
O
= 0mA
t
RC
=
t
RC
(min)
t
CK
≥
t
(min)
I
O
= 0mA
t
RC
=
t
RC
(min)
t
CK
≥
t
CK
(min)
I
O
= 0mA
t
RC
=
t
RC
(min)
t
CK
≥
t
(min)
I
O
= 0mA
90ns
90ns
90ns
120ns
105ns
100ns
180ns
135ns
110ns
300ns
195ns
160ns
t
RC
=
∞
t
CK
= 30ns
t
RC
=
∞
t
CK
= 15ns
t
RC
=
∞
t
CK
= 10ns
t
RC
=
∞
t
CK
= 30ns
t
RC
=
∞
t
CK
= 15ns
t
RC
=
∞
t
CK
= 10ns
mA
1, 2
I
DD6
Operating Current
Burst Length = 2
mA
1, 2, 3
I
DD7
Operating Current
Burst Length = 4
mA
1, 2, 3
I
DD8
Operating Current
Burst Length = 8
mA
1, 2, 3
I
DD9
Operating Current
Burst Length = Full Page
t
RC
=
Infinity
t
CK
≥
t
(min)
I
O
= 0mA
CL=1
-10
220
mA
1, 2, 3
CL=2
-10
360
CL=3
-10
540
I
DD10
Operating Current
1N Rule
(Continuous Read/Write
cycles with new column
address registered each
clock cycle)
t
RC
=
Infinity
t
CK
≥
t
CK
(min)
I
O
= 0mA
CL=1
-10
360
mA
1, 2
CL=2
-10
560
CL=3
-10
760
I
DDA
Serial PD Device Active
Power Supply
Current
SCL Clock Frequency = 100kHz
1.0
mA
4
1. The specified values are obtained with the output open.
2. The specified values are valid when addresses and DQs are changed no more than once during t
CK
(min).
3. The specified values are obtained when the programmed burst length is executed to completion without interruption by a
subsequent burst Read or Write cycle.
4. Input pulse levels V
DD
x 0.1 to V
DD
x 0.9, input rise and fall times 10ns, input and output timing levels V
DD
x 0.5, output
load 1 TTL gate and CL = 100pf.
Discontinued (12/98 - last order; 9/99 last ship)
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