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參數(shù)資料
| 型號(hào)： | IBM13T4644MPC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(4M x 64小外形雙列直插同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 4米× 64 SDRAM的內(nèi)存蘇（小外形雙列直插內(nèi)存模塊）（4米× 64小外形雙列直插同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 273K |
| 代理商： | IBM13T4644MPC |
IBM13T4644MPC
4M x 64 SDRAM SO DIMM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 14
29L6293.E93850A
3/99
Common Parameters
Symbol
Parameter
10
Units
Notes
Min.
Max.
t
CS
Command Setup Time
3
—
ns
t
CH
Command Hold Time
1
—
ns
t
AS
Address and Bank Select Set-up Time
3
—
ns
t
AH
Address and Bank Select Hold Time
1
—
ns
t
RCD
RAS to CAS Delay
30
—
ns
1
t
RC
Bank Cycle Time
90
ns
1
t
RAS
Active Command Period
60
100000
ns
1
t
RP
Precharge Time
30
—
ns
1
t
RRD
Bank to Bank Delay Time
20
—
ns
1
t
CCD
CAS to CAS Delay Time
1
—
CK
t
RSC
Mode Register Set Cycle Time
20
—
ns
1
1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the
number of clock cycles
=
specified value of timing / clock period (count fractions as a whole number).
Refresh Cycle
Symbol
Parameter
10
Units
Notes
Min.
Max.
t
REF
Refresh Period
—
64
ms
1
t
SREX
Self Refresh Exit Time
10
—
ns
1. 4096 cycles.
Read Cycle
Symbol
Parameter
10
Units
Notes
Min.
Max.
t
OH
Data Out Hold Time
3
—
ns
t
LZ
Data Out to Low Impedance Time
0
—
ns
t
HZ3
Data Out to High Impedance Time
3
7
ns
1
t
HZ2
Data Out to High Impedance Time
3
8
ns
1
t
DQZ
DQM Data Out Disable Latency
2
—
CK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels
Discontinued (8/99 - last order; 12/99 - last ship)
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| IBM13T4644MPD | One Bank 4M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(1組 4M x 64 PC100小外形雙列直插同步動(dòng)態(tài)RAM模塊) |
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