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參數(shù)資料
| 型號(hào)： | IBM13T4644MPC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(4M x 64小外形雙列直插同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 4米× 64 SDRAM的內(nèi)存蘇（小外形雙列直插內(nèi)存模塊）（4米× 64小外形雙列直插同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 273K |
| 代理商： | IBM13T4644MPC |
IBM13T4644MPC
4M x 64 SDRAM SO DIMM
29L6293.E93850A
3/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 14
Functional Description and Timing Diagrams
Refer to the IBM 64Mb Synchronous DRAM data sheet, document 19L3264.E35855A for the functional
description and timing diagrams for SDRAM operation.
Refer to the IBM Application Notes: Serial Presence Detect on Memory DIMMsand SDRAM Presence Detect
Definitions for the Serial Presence Detect functional description and timings.
All AC timing information refers to the timings at the SDRAM devices.
Write Cycle
Symbol
Parameter
10
Units
Min.
Max.
t
DS
Data In Set-up Time
3
—
ns
t
DH
Data In Hold Time
1
—
ns
t
DPL3
Data input to Precharge, CL
=
3
10
—
ns
t
DPL2
Data input to Precharge, CL
=
2
15
—
ns
t
DQW
DQM Write Mask Latency
0
—
CK
Presence Detect Read and Write Cycle
Symbol
Parameter
Min.
Max.
Units
Notes
f
SCL
SCL Clock Frequency
100
kHz
T
I
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
t
AA
SCL Low to SDA Data Out Valid
0.3
3.5
μ
s
t
BUF
Time the Bus Must Be Free before a New Transmission Can Start
4.7
μ
s
t
HD:STA
Start Condition Hold Time
4.0
μ
s
t
LOW
Clock Low Period
4.7
μ
s
t
HIGH
Clock High Period
4.0
μ
s
t
SU:STA
Start Condition Setup Time (for a Repeated Start Condition)
4.7
μ
s
t
HD:DAT
Data in Hold Time
0
μ
s
t
SU:DAT
Data in Setup Time
250
ns
t
r
SDA and SCL Rise Time
1
μ
s
t
f
SDA and SCL Fall Time
300
ns
t
SU:STO
Stop Condition Setup Time
4.7
μ
s
t
DH
Data Out Hold Time
300
ns
t
WR
Write Cycle Time
15
ms
1
1. The Write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal Erase/Program
cycle. During the Write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resis-
tor, and the device does not respond to its slave address.
Discontinued (8/99 - last order; 12/99 - last ship)
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