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參數(shù)資料
| 型號： | IBM13T4644MPC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(4M x 64小外形雙列直插同步動態(tài)RAM模塊) |
| 中文描述： | 4米× 64 SDRAM的內(nèi)存蘇（小外形雙列直插內(nèi)存模塊）（4米× 64小外形雙列直插同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 273K |
| 代理商： | IBM13T4644MPC |
IBM13T4644MPC
4M x 64 SDRAM SO DIMM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 14
29L6293.E93850A
3/99
Operating, Standby and Refresh Currents
(T
A
=
0 to
+
70
°
C, V
DD
=
3.3V
±
0.3V)
Parameter
Symbol
Test Condition
Current
Units
Notes
Operating Current
t
RC
=
t
RC
(min), t
CK
=
min
Active-Precharge command cycling
without Burst operation
I
DD1
1 bank operation
220
mA
1, 2
Precharge Standby Current in Power
Down Mode
I
DD2P
CKE
≤
V
IL
(max), t
CK
=
min, S0
=
V
IH
(min)
4
mA
I
DD2Ps
CKE
≤
V
IL
(max), t
CK
=
Infinity, S0
=
V
IH
(min)
4
mA
Precharge Standby Current in Non-
Power Down Mode
I
DD2N
CKE
≥
V
IH
(min), t
CK
=
min, S0
=
V
IH
(min)
100
mA
5
I
DD2NS
CKE
≥
V
IH
(min), t
CK
=
Infinity, S0
=
V
IH
(min)
20
mA
8
No Operating Current
(Active state: 4 bank)
I
DD3N
CKE
≥
V
IH
(min), t
CK
=
min, S0
=
V
IH
(min)
120
mA
5
I
DD3P
CKE
≤
V
IL
(max), t
CK
=
min, S0
=
V
IH
(min)
(Power Down Mode)
28
mA
7
Burst Operating Current
I
DD4
t
CK
=
min, Read/ Write command cycling
360
mA
2, 6
Auto (CBR) Refresh Current
I
DD5
t
CK
=
min, CBR command cycling
440
mA
Self Refresh Current
I
DD6
CKE0
≤
0.2V
1.6
mA
Serial PD Device Standby Current
I
SB5
V
IN
=
GND or V
DD
10
μ
A
3
Serial PD Device Active Power Supply
Current
I
CCA
SCL Clock Frequency
=
100KHz
1
mA
4
1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t
CK
and t
RC
.
Input signals are changed once during t
CK
(min).
2. The specified v(alues are obtained with the output open.
3. V
DD
=
3.3V.
4. Input pulse levels V
DD
x 0.1 to V
DD
x 0.9, input rise and fall times 10ns, input and output timing levels V
DD
x 0.5, output load 1 TTL
gate and CL
=
100pf.
5. Input signals are changed once during three clock cycles.
6. Input signals are changed once during t
CK
(min).
7. Active Standby current will be higher if clock suspend is entered during a Burst Read cycle (add 1mA per DQ).
8. Input signals are stable.
Discontinued (8/99 - last order; 12/99 - last ship)
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