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參數(shù)資料
| 型號： | IBM13T4644MPD |
| 廠商： | IBM Microeletronics |
| 英文描述： | One Bank 4M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(1組 4M x 64 PC100小外形雙列直插同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 一位銀行分蘇× 64 SDRAM的內(nèi)存（小外形雙列直插內(nèi)存模塊）（1組4米× 64 PC100的小外形雙列直插同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 4/18頁 |
| 文件大小： | 271K |
| 代理商： | IBM13T4644MPD |
IBM13T4644MPE
IBM13T4644MPD
One Bank 4M x 64 SDRAM SO DIMM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 18
45L7126.E93903A
5/99
Input/Output Functional Description
Symbol
Type
Signal
Polarity
Function
CK0
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of their
associated clock.
CKE0
Input
Level
Active High
Activates the CK0 signal when high and deactivates it when low.
By deactivating the clock, CKE0 low initiates the Power Down mode, Suspend mode, or
the Self Refresh mode.
S0
Input
Pulse
Active Low
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
RAS, CAS
WE
Input
Pulse
Active Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
BA0
Input
Level
—
Selects which SDRAM bank is to be active.
A0-A9,A11,
A10/AP
Input
Level
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A7 defines the column address (CA0-CA8)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high,
autoprecharge is selected and BA0 defines the bank to be precharged (low=bank A,
high=bank B). If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0 to control which
bank(s) to precharge. If AP is high, both bank A and bank B will be precharged regard-
less of the state of BA0. If AP is low, then BA0 is used to define which bank to precharge.
DQ0 - DQ63
Input
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DQMB0 -
DQMB7
Input
Pulse
Active High
The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a byte mask by allowing input data to be written if it is low but blocks the write operation if
DQM is high.
V
CC
, V
SS
Supply
Power and ground for the module.
Discontinued (4/1/00 last order; 7/31/00 - last ship)
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