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參數(shù)資料
| 型號： | IBM13T8644HPC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Modules）(8M x 64 144腳小外形雙列直插同步動態(tài)RAM模塊) |
| 中文描述： | 8米× 64 SDRAM的內(nèi)存蘇（小外形雙列直插式內(nèi)存模塊）（8米× 64 144腳小外形雙列直插同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 325K |
| 代理商： | IBM13T8644HPC |
IBM13T8644HPB
IBM13T8644HPC
8M x 64 SDRAM SO DIMM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 17
01L5951.E24562B
5/99
AC Characteristics
(T
A
=
0 to
+
70
°
C, V
DD
=
3.3V
±
0.3V)
1. An initial pause of 200
μ
s, with DQMB0-7 and CKE0 held high, is required after power-up. A Precharge All
Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after
the Mode Register Set operation.
2. The Transition time is measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
3. In addition to meeting the transition rate specification, the CK0, CK2, and CKE0 signals must transit
between V
IH
and V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
4. Load Circuit A: AC timing tests have V
IL
=
0.4 V and V
IH
=
2.4 V with the timing referenced to the 1.40V
crossover point.
5. Load Circuit A: AC measurements assume t
T
=
1.0 ns.
6. Load Circuit B: AC timing tests have V
IL
=
0.8 V and V
IH
=
2.0 V with the timing referenced to the 1.40V
crossover point.
7. Load Circuit B: AC measurements assume t
T
=
1.2 ns.
AC Characteristics Diagrams
Clock and Clock Enable Parameters
Symbol
Parameter
10
Units
Notes
Min.
Max.
t
CK3
t
CK2
t
AC3 (A)
t
AC2 (A)
t
AC3 (B)
t
AC2 (B)
t
CKH
t
CKL
t
CES
t
CEH
t
SB
t
T
Clock Cycle Time, CAS Latency
=
3
10
1000
ns
Clock Cycle Time, CAS Latency
=
2
15
1000
ns
Clock Access Time, CAS Latency
=
3
—
7
ns
1
Clock Access Time, CAS Latency
=
2
—
8
ns
1
Clock Access Time, CAS Latency
=
3
—
9
ns
2
Clock Access Time, CAS Latency
=
2
—
9
ns
2
Clock High Pulse Width
3
—
ns
3
Clock Low Pulse Width
3
—
ns
3
Clock Enable Setup Time
3
—
ns
Clock Enable Hold Time
1
—
ns
Power down mode Entry Time
0
10
ns
Transition Time (Rise and Fall)
0.5
10
ns
1. Access time is measured at 1.4V. In AC Characteristics section, see notes 1, 2, 3, 4, and 5, and load circuit A.
2. Access time is measured at 1.4V. In AC Characteristics section, see notes 1, 2, 3, 6, and 7, and load circuit B.
3. t
CKH
is the pulse width of CK measured from the positive edge to the negative edge referenced to V
IH
(min). t
CKL
is the pulse width
of CK measured from the negative edge to the positive edge referenced to V
IL
(max).
Output
Input
Clock
t
OH
t
SETUP
t
HOLD
t
AC
t
LZ
1.4V
1.4V
V
IL
1.4V
t
T
V
tt
=
1.4V
Output
50
50pF
Z
o
=
50
AC Output Load Circuit (A)
t
CKH
t
CKL
Output
50pF
Z
o
=
50
AC Output Load Circuit (B)
V
Discontinued (8/99 - last order; 12/99 - last ship)
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