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參數(shù)資料
| 型號： | IBM13T8644HPC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Modules）(8M x 64 144腳小外形雙列直插同步動態(tài)RAM模塊) |
| 中文描述： | 8米× 64 SDRAM的內存蘇（小外形雙列直插式內存模塊）（8米× 64 144腳小外形雙列直插同步動態(tài)內存模塊） |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 325K |
| 代理商： | IBM13T8644HPC |
IBM13T8644HPB
IBM13T8644HPC
8M x 64 SDRAM SO DIMM
01L5951.E24562B
5/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 17
Serial Presence Detect
(Part 1 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
80
08
04
0C
09
01
4000
01
A0
70
00
80
08
00
01
8F
04
06
01
01
00
Notes
0
1
2
3
4
5
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Banks
Data Width of Assembly
Voltage Interface Level of this Assembly
SDRAM Device Cycle Time at CL
=
3
SDRAM Device Access Time from Clock at CL=3
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Device Width
Error Checking SDRAM Device Width
SDRAM Device Attr: Min CK Delay, Random Col Access
SDRAM Device Attributes: Burst Lengths Supported
SDRAM Device Attributes: Number of Device Banks
SDRAM Device Attributes: CAS Latencies Supported
SDRAM Device Attributes: CS Latency
SDRAM Device Attributes: WE Latency
SDRAM Module Attributes
128
256
SDRAM
12
9
1
x64
LVTTL
10.0ns
7.0ns
Non-Parity
SR/1x(15.625
μ
s)
x8
N/A
1 Clock
1,2,4,8, Full Page
4
2, 3
0
0
Unbuffered
Wr-1/Rd Burst, Precharge All,
Auto-Precharge, V
DD
±
10%
15.0ns
8.0ns
N/A
N/A
6 - 7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SDRAM Device Attributes: General
0E
23
24
25
26
Minimum Clock Cycle at CL=2
Maximum Data Access Time (t
AC
) from Clock at CL=2
Minimum Clock Cycle Time at CL=1
Maximum Data Access Time (t
AC
) from Clock at CL=1
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse width (t
RAS
)
Module Bank Density
Address and Command Setup Time Before Clock
Address and Command Hold Time After Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
36 - 61 Reserved
62
SPD Revision
63
Checksum for bytes 0 - 62
64 - 71 Manufacturers’ JEDEC ID Code
F0
80
00
00
27
30ns
1E
28
20ns
14
29
30ns
1E
30
31
32
33
34
35
60ns
64MB
3.0
1.0
3.0
1.0
Undefined
2
Checksum Data
IBM
3C
10
30
10
30
10
00
02
cc
1
A400000000000000
1. cc = Checksum Data byte, 00-FF (Hex)
2. “R” = Alphanumeric revision code, A-Z, 0-9
3. rr = ASCII coded revision code byte “R”
4. yy = Binary coded decimal year code, 00-99 (Decimal)
‘
00-63 (Hex)
5. ww = Binary coded decimal week code, 01-53 (Decimal)
‘
01-35 (Hex)
6. ss = Serial number data byte, 00-FF (Hex)
Discontinued (8/99 - last order; 12/99 - last ship)
相關PDF資料 |
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|---|---|
| IBM13T8644HPD | One Bank 8M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(1組 8M x 64 PC100小外形雙列直插同步動態(tài)RAM模塊) |
| IBM13T8644HPE | One Bank 8M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(1組 8M x 64 PC100小外形雙列直插式同步動態(tài)RAM模塊) |
| IBM13T8644MPD | Two Bank 8M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(2組 8M x 64 PC100小外形雙列直插同步動態(tài)RAM模塊) |
| IBM13T8644MPE | 8M x 64 PC100 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(8M x 64 PC100小外形雙列直插式同步動態(tài)RAM模塊) |
| IBM13V25649AN | 256K x 64 SGRAM SO DIMM（Small Outline Dual In-line Memory Modules）(256K x 64 144腳小外形雙列直插同步圖形RAM模塊) |
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