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參數(shù)資料
| 型號： | IBM13T8644HPE |
| 廠商： | IBM Microeletronics |
| 英文描述： | One Bank 8M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(1組 8M x 64 PC100小外形雙列直插式同步動態(tài)RAM模塊) |
| 中文描述： | 一位銀行8米× 64 SDRAM的內(nèi)存蘇（小外形雙列直插內(nèi)存模塊）（1組8米× 64 PC100的小外形雙列直插式同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 281K |
| 代理商： | IBM13T8644HPE |
IBM13T8644HPD
IBM13T8644HPE
One Bank 8M x 64 SDRAM SO DIMM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 18
45L7125.E93903A
5/99
AC Characteristics
(T
A
= 0 to +70
°
C, V
DD
= 3.3V
±
0.3V)
1. An initial pause of 100
μ
s is required after power-up, then a Precharge All Banks command must be given
followed by a minimum of two Auto (CBR) Refresh cycles before the Mode Register Set operation can
begin.
2. AC timing tests have V
IL
= 0.8V and V
IH
= 2.0V with the timing referenced to the 1.40V crossover point.
3. The Transition time is measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
4. AC measurements assume t
T
=1ns.
5. In addition to meeting the transition rate specification, the clock and CKEn must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
AC Characteristics Diagrams
Clock and Clock Enable Parameters
Symbol
Parameter
-10
Units
Notes
Min.
Max.
t
CK3
Clock Cycle Time, CAS Latency = 3
10
1000
ns
t
CK2
Clock Cycle Time, CAS Latency = 2
15
1000
ns
1
t
AC3
Clock Access Time, CAS Latency = 3
—
7
ns
2
t
AC2
Clock Access Time, CAS Latency = 2
—
8
ns
2
t
CKH
Clock High Pulse Width
3
—
ns
3
t
CKL
Clock Low Pulse Width
3
—
ns
3
t
CES
Clock Enable Set-up Time
3
—
ns
t
CEH
Clock Enable Hold Time
1
—
ns
t
SB
Power down mode Entry Time
0
10
ns
t
T
Transition Time (Rise and Fall)
0.5
10
ns
1. For 66MHz clock, CAS Latency = 2.
2. Access time is measured at 1.4V. See AC output load circuit above.
3. t
CKH
is the pulse width of CK measured from the positive edge to the negative edge referenced to V
IH
(min). t
CKL
is the pulse width
of CK measured from the negative edge to the positive edge referenced to V
IL
(max).
Output
Input
Clock
t
OH
t
SETUP
t
HOLD
t
AC
t
LZ
1.4V
0.8V
1.4V
1.4V
2.0V
t
T
Vtt=1.4V
Output
50
50pF
Z
o
= 50
AC Output Load Circuit
Discontinued (4/1/00 last order; 7/31/00 - last ship)
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