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參數(shù)資料
| 型號： | IBM13T8644HPE |
| 廠商： | IBM Microeletronics |
| 英文描述： | One Bank 8M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(1組 8M x 64 PC100小外形雙列直插式同步動態(tài)RAM模塊) |
| 中文描述： | 一位銀行8米× 64 SDRAM的內存蘇（小外形雙列直插內存模塊）（1組8米× 64 PC100的小外形雙列直插式同步動態(tài)內存模塊） |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 281K |
| 代理商： | IBM13T8644HPE |
IBM13T8644HPD
IBM13T8644HPE
One Bank 8M x 64 SDRAM SO DIMM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 18
45L7125.E93903A
5/99
Read Cycle
Symbol
Parameter
-10
Units
Notes
Min.
Max.
t
OH
Data Out Hold Time
3
—
ns
t
LZ
Data Out to Low Impedance Time
0
—
ns
t
HZ3
Data Out to High Impedance Time
3
6
ns
1
t
HZ2
Data Out to High Impedance Time
3
8
ns
1
t
DQZ
DQM Data Out Disable Latency
2
—
CLK
1. .Referenced to the time at which the output achieves the open circuit condition, not to output voltage levells.
Refresh Cycle
Symbol
Parameter
-10
Units
Notes
Min.
Max.
t
REF
Refresh Period
—
64
ms
1
t
SREX
Self Refresh Exit Time
10
ns
1. 4096 auto refresh cycles.
Write Cycle
Symbol
Parameter
-10
Units
Min.
Max.
t
DS
Data In Set-up Time
3
—
ns
t
DH
Data In Hold Time
1
—
ns
t
DPL
Data Input to Precharge
15
—
ns
t
DAL3
Data In to Active Delay
CAS Latency = 3
4
CLK
t
DAL2
Data In to Active Delay
CAS Latency = 2
3
CLK
t
DQW
DQM Write Mask Latency
0
—
CLK
Discontinued (4/1/00 last order; 7/31/00 - last ship)
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