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參數(shù)資料
| 型號： | IBM13T8644HPE |
| 廠商： | IBM Microeletronics |
| 英文描述： | One Bank 8M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(1組 8M x 64 PC100小外形雙列直插式同步動態(tài)RAM模塊) |
| 中文描述： | 一位銀行8米× 64 SDRAM的內存蘇（小外形雙列直插內存模塊）（1組8米× 64 PC100的小外形雙列直插式同步動態(tài)內存模塊） |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 281K |
| 代理商： | IBM13T8644HPE |
IBM13T8644HPD
IBM13T8644HPE
One Bank 8M x 64 SDRAM SO DIMM
45L7125.E93903A
5/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 18
Operating, Standby and Refresh Currents
(T
A
= 0 to +70C, V
DD
= 3.3V
±
0.3V)
Parameter
Symbol
Test Condition
Speed
Units
Notes
-10
Operating Current
t
RC
=
t
RC
(min), t
CK
= min
Active-Precharge command cycling without Burst
operation
I
DD1
1 bank operation
440
mA
1, 2
Precharge Standby Current in Power
Down Mode
I
DD2P
CKE
≤
V
IL
(max), t
CK
= min, S0, S1 =V
IH
(min)
8
mA
I
DD2Ps
CKE
≤
V
IL
(max), t
CK
= Infinity, S0, S1 =V
IH
(min)
8
mA
Precharge Standby Current in Non-Power
Down Mode
I
DD2N
CKE
≥
V
IH
(min), t
CK
= min, S0, S1 =V
IH
(
min)
200
mA
3
I
DD2NS
CKE
≥
V
IH
(min), t
CK
= Infinity, S0, S1 =V
IH
(min)
48
mA
No Operating Current (Active state: 4 bank)
I
DD3N
CKE
≥
V
IH
(min), t
CK
= min, S0, S1 =V
IH
(min)
240
mA
3
I
DD3P
CKE
≤
V
IL
(max), t
CK
= min,
S0, S1 =V
IH
(min)(Power Down Mode)
24
mA
Burst Operating Current
I
DD4
t
CK
= min, Read/ Write command cycling
720
mA
2, 3
Auto (CBR) Refresh Current
I
DD5
t
CK
= min, CBR command cycling
880
mA
4
Self Refresh Current
I
DD6
CKE0
≤
0.2V
3.2
mA
4
Serial PD Device Standby Current
I
SB5
V
IN
= GND or V
DD
30
μ
A
5
Serial PD Device Active Power Supply Current
I
CCA
SCL Clock Frequency = 100KHz
1
mA
6
1. Input signals are changed up to three times during t
RC
(min). This assumes the 14 Row Address mode with four-bank operation
using rows A0-A11 and BA0-BA1.
2. The specified values are obtained with the output open.
3. Input signals are changed once during three clock cycles.
4. 64ms refresh time (15.6
μ
s, 4K refresh).
5. V
DD
= 3.3V.
6. As follows:Input pulse levels V
DD
x 0.1 to V
DD
x 0.9, Input rise and fall times 10ns, Input and output timing levels V
DD
x 0.5, Output
load 1 TTL gate and CL=100pf.
Discontinued (4/1/00 last order; 7/31/00 - last ship)
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