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參數(shù)資料
| 型號： | IBM13T8644MPE |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 64 PC100 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(8M x 64 PC100小外形雙列直插式同步動態(tài)RAM模塊) |
| 中文描述： | 8米× 64蘇PC100的SDRAM的內(nèi)存（小外型雙線內(nèi)存模組）（8米× 64 PC100的小外形雙列直插式同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 437K |
| 代理商： | IBM13T8644MPE |
IBM13T8644MPE
Preliminary
8M x 64 PC100 SDRAM SO DIMM
45L7072.E93888B
5/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 17
Clock Frequency and Latency
Symbol
f
CK
t
CK
t
AA
t
RP
t
RCD
t
RC
t
RAS
t
DPL
t
DAL
t
RRD
t
CCD
t
WL
t
DQW
t
DQZ
t
CSL
Parameter
Units
MHz
Clock Frequency
100
66
Clock Cycle Time
10
15
ns
CAS Latency
Precharge Time
3
2
CLK
2
2
CLK
RAS to CAS Delay
Bank Cycle Time
2
2
CLK
7
6
CLK
Minimum Bank Active Time
5
4
CLK
Data In to Precharge
2
1
CLK
Data In to Active/Refresh
5
3
CLK
Bank to Bank Delay Time
2
2
CLK
CAS to CAS Delay Time
Write Latency
1
1
CLK
0
0
CLK
DQM Write Mask Latency
0
0
CLK
DQM Data Disable Latency
2
2
CLK
Clock Suspend Latency
1
1
CLK
Presence Detect Read and Write Cycle
Symbol
f
SCL
T
I
t
AA
Parameter
Min
Max
100
Unit
kHz
Notes
SCL Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
SCL Low to SDA Data Out Valid
0.3
3.5
μ
s
t
BUF
Time the Bus Must Be Free before a New Transmission Can Start
4.7
μ
s
t
HD:STA
Start Condition Hold Time
4.0
μ
s
t
LOW
Clock Low Period
4.7
μ
s
t
HIGH
Clock High Period
4.0
μ
s
t
SU:STA
Start Condition Setup Time (for a Repeated Start Condition)
4.7
μ
s
t
HD:DAT
t
SU:DAT
t
r
t
f
t
SU:STO
t
DH
t
WR
Data in Hold Time
0
μ
s
ns
Data in Setup Time
250
SDA and SCL Rise Time
1
μ
s
ns
SDA and SCL Fall Time
300
Stop Condition Setup Time
4.7
μ
s
ns
Data Out Hold Time
300
Write Cycle Time
15
ms
1
1. The Write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal Erase/Program
cycle. During the Write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resis-
tor, and the device does not respond to its slave address.
Discontinued (4/1/00 last order; 7/31/00 - last ship)
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