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| 型號(hào)： | IBM13T8644MPE |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 64 PC100 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(8M x 64 PC100小外形雙列直插式同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 8米× 64蘇PC100的SDRAM的內(nèi)存（小外型雙線內(nèi)存模組）（8米× 64 PC100的小外形雙列直插式同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 9/17頁(yè) |
| 文件大小： | 437K |
| 代理商： | IBM13T8644MPE |
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IBM13T8644MPE
Preliminary
8M x 64 PC100 SDRAM SO DIMM
45L7072.E93888B
5/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 17
Operating, Standby and Refresh Currents
(T
A
= 0 to +70C, V
DD
= 3.3V
±
0.3V)
Parameter
Symbol
Test Condition
Speed/Organization
Units
Notes
-360/8Mx64
Operating Current
t
RC
=
t
RC
(min), t
CK
= min
Active-Precharge command cycling
without Burst operation
I
DD1
1 bank operation
400
mA
1, 3, 4
Precharge Standby Current in
Power Down Mode
I
DD2P
CKE
≤
V
IL
(max), t
CK
= min, S0, S1
=V
IH
(min)
8
mA
2
I
DD2Ps
CKE
≤
V
IL
(max), t
CK
= Infinity, S0, S1
=V
IH
(min)
8
mA
2
Precharge Standby Current in Non-
Power Down Mode
I
DD2N
CKE
≥
V
IH
(min), t
CK
= min, S0, S1 =V
IH
(
min)
200
mA
2, 5
I
DD2NS
CKE
≥
V
IH
(min), t
CK
= Infinity, S0, S1
=V
IH
(min)
48
mA
2
No Operating Current
(Active state: 4 bank)
I
DD3N
CKE
≥
V
IH
(min), t
CK
= min, S0, S1 =V
IH
(
min)
240
mA
2, 5
I
DD3P
CKE
≤
V
IL
(max), t
CK
= min, S0, S1 =V
IH
(
min) (Power Down Mode)
24
mA
2
Burst Operating Current
I
DD4
t
CK
= min, Read/ Write command
cycling
480
mA
1, 4, 5
Auto (CBR) Refresh Current
I
DD5
t
CK
= min, CBR command cycling
680
mA
1, 6
Self Refresh Current
I
DD6
CKE0
≤
0.2V
3.2
mA
1, 6
Serial PD Device Standby Current
I
SB5
V
IN
= GND or V
DD
30
μ
A
7
Serial PD Device Active Power Sup-
ply Current
I
CCA
SCL Clock Frequency = 100KHz
1
mA
8
1. The specified values are for one SO DIMM bank in the specified mode and the other SO DIMM bank in Active Standby (I
CC3N
).
2. The specified values are for both SO DIMM banks operating in the specified mode.
3. Input signals are changed up to three times during t
RC
(min). This assumes the 14 Row Address mode with four-bank operation
using rows A0-A11 and BA0-BA1.
4. The specified values are obtained with the outputs open.
5. Input signals are changed once during three clock cycles.
6. 64ms refresh time (15.6
μ
s, 4K refresh).
7. V
DD
= 3.3V.
8. Input pulse levels V
DD
x 0.1 to V
DD
x 0.9, Input rise and fall times 10ns, Input and output timing levels V
DD
x 0.5, Output load 1 TTL
gate and CL=100pf
Discontinued (4/1/00 last order; 7/31/00 - last ship)
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