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| 型號： | IBM13V25649AN |
| 廠商： | IBM Microeletronics |
| 英文描述： | 256K x 64 SGRAM SO DIMM（Small Outline Dual In-line Memory Modules）(256K x 64 144腳小外形雙列直插同步圖形RAM模塊) |
| 中文描述： | 256K × 64 SGRAM蘇內(nèi)存（小外形雙列直插式內(nèi)存模塊）（256K × 64 144腳小外形雙列直插同步圖形內(nèi)存模塊） |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 224K |
| 代理商： | IBM13V25649AN |
IBM13V25649AN IBM13V51649AN
256K/512K x 64 SGRAM SO DIMM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 14
88H4121.E24358
Revised 1/98
Functional Description and Timing Diagrams
Refer to the IBM 256Kx32 Synchronous SGRAM datasheet (GA15-5256-00) for the functional description
and timing diagrams for SGRAM operation.
Timing Specifications
Note: all AC timing information below refers to SGRAM device timings.
So DIMM level XTK/IBIS models are available to perform system level
simulation and timing analysis.
CAS
Latency
-7R5
-10
Units
Symbol
t
AC3for 50 pF
load
t
AC2for 50 pF
load
Parameter
Min
-
Max
7
Min
-
Max
9
Access time from CLK (positive edge)
3
ns
2
-
10
-
12
t
AH
t
AS
t
BPL
t
BWC
t
CH
t
CHI
t
CK3
t
CK2
t
CKH
t
CKS
t
CL
t
CS
t
DH
t
DS
t
HZ
t
LZ
t
MTC
t
OH
t
RAS
t
RC
t
RCD
t
REF
t
REF
t
RP
t
RRD
t
SML
t
T
t
WR
t
XSR
Address hold time
1.5
-
1.5
-
ns
Address setup time
2.5
-
2.5
-
ns
Block Write to Precharge delay
7.5
-
10
-
ns
Block Write cycle time
7.5
-
10
-
ns
CS, RAS, CAS, WE, DSF, DQM hold time
1.0
-
1.0
-
ns
CLK high level width
3
-
3.5
-
ns
System clock cycle time
3
7.5
-
10
-
ns
2
12
-
15
-
CKE hold time
1.0
-
1.0
-
ns
CKE setup time
2.5
-
2.5
-
ns
CLK low level width
3
-
3.5
-
ns
CS, RAS, CAS, WE, DSF, DQM setup time
2.5
-
2.5
-
ns
Date-in hold time
1.5
-
1.5
-
ns
Data-in setup time
2.5
-
2.5
-
ns
Data-out high impedance time
3.5
10
3.5
10
ns
Data-out low impedance time
3
-
3
-
ns
Load Mode Register command to command
1
-
1
-
t
CK
ns
Data-out hold time
3.5
-
3.5
-
Active to Precharge command period
45
120K
60
120K
ns
Auto Refresh and Active to Active command period
67.5
-
90
-
ns
Active to Read, Write or Block Write delay
22.5
-
30
-
ns
Refresh Period (1024 cycles) for Non Self-Refresh parts
-
16
-
16
ms
Refresh Period (1024 cycles) for Self-Refresh parts
-
128
-
128
ms
Row Precharge time
22.5
-
30
-
ns
Active bank A to Active bank B command period
7.5
-
10
-
ns
Load Special Mode Register command to command
1
-
1
-
t
CK
ns
Transition time
1
30
1
30
Write recovery time
7.5
-
10
-
ns
Exit Self Refresh to Active command
100
-
100
-
ns
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