
IBM2520L8767
IBM Processor for ATM Resources
atmrm.toc.01
08/27/99
Table of Contents
Page xi
Clock & Power Management ..........................................................................................................357
Processor Local Bus(PLB) ............................................................................................................. 357
Bridge ............................................................................................................................................. 357
SRAM ............................................................................................................................................. 357
Control Memory .............................................................................................................................. 357
Packet Memory ............................................................................................................................... 357
PCI Master Interface-External ........................................................................................................ 357
IBM2520L8767 Register Space ...................................................................................................... 357
PCI Slave Interface ......................................................................................................................... 358
Address Translation Examples ....................................................................................................... 358
PCORE Control Register ................................................................................................................ 358
PCORE Status Register .................................................................................................................360
PCORE User Status Register ......................................................................................................... 361
PCORE 401 External Status Register ............................................................................................362
PCORE IBM2520L8767 Shadow Status Register .......................................................................... 363
PCORE IBM2520L8767 Shadow Rxque Status Register .............................................................. 363
PCORE Interrupt Enable Register .................................................................................................. 364
PCORE User Interrupt Enable ........................................................................................................ 364
PCORE 401 Interrupt Enable Register ........................................................................................... 364
PCORE Error Lock Enable Register ............................................................................................... 365
PCORE User Error Lock Enable Register ...................................................................................... 365
PCORE Transaction Dead Man Timer Value Register ................................................................... 365
PCORE Address Translation Base Address Array .........................................................................366
PCORE Address Transaction Type and Range Array ....................................................................367
PCORE Last PLB Address Register ............................................................................................... 368
PCORE Last PLB Error Register .................................................................................................... 369
PCORE SRAM ............................................................................................................................... 370
PCORE SRAM Base Address ........................................................................................................ 370
PCORE Read Data Transfer Registers .......................................................................................... 371
PCORE Write Data Transfer Registers .......................................................................................... 371
PCORE IBM2520L8767 Polling Register .......................................................................................372
PCORE Integer Input Rate Conversion Register ...........................................................................372
PCORE ABR Output Rate Register ................................................................................................ 373
PLB PACR Register ....................................................................................................................... 373
RS-232 Interface Logic (RS-232) ........................................................................................................ 374
RS-232 Line Status Register ..........................................................................................................374
RS-232 Handshake Status Register ............................................................................................... 375
RS-232 Baud Rate Divisor High Register .......................................................................................376
RS-232 Baud Rate Divisor Low Register .......................................................................................376
RS-232 Serial Port Control Register ............................................................................................... 377
RS-232 Receive Command Register ............................................................................................. 378
RS-232 Transmit Command Register ............................................................................................379
RS-232 Byte Transmit/Receive Buffer ............................................................................................380
RS-232 Mode Register ................................................................................................................... 381
RS-232 Four Byte Transmit/Receive Buffer ................................................................................... 382
Reset and Power-on Logic (CRSET) ................................................................................................. 383
Reset Status Register ..................................................................................................................... 383
Software Reset Enable Register .................................................................................................... 384
Software Reset Register .................................................................................................................384
Memory Type Register ................................................................................................................... 385
CRSET PLL Range Debug .............................................................................................................386
CRSET Control Register ................................................................................................................ 387