
IBM2520L8767
IBM Processor for ATM Resources
atmrm.toc.01
08/27/99
Table of Contents
Page i
Table of Contents
Features .............................................................................................................................1
Description ........................................................................................................................1
ATM Subsystem Block Diagram ......................................................................................1
Conventions ......................................................................................................................2
Ordering Information ........................................................................................................2
Standards Compliance .....................................................................................................3
Environmental Ratings .....................................................................................................4
Absolute Maximum Ratings ................................................................................................................... 4
Recommended Operating Conditions ................................................................................................... 4
Power Dissipation ................................................................................................................................... 4
Package Diagram .................................................................................................................................... 5
Pinout Viewed from Above .....................................................................................................................6
Ground Pin Locations ............................................................................................................................. 6
Pinout Viewed from Below .....................................................................................................................7
V
DD
Pin Locations ................................................................................................................................... 7
Block Diagram ......................................................................................................................................... 8
Functional Description .....................................................................................................9
Subsystem Blocks ................................................................................................................................ 10
External Architecture ............................................................................................................................ 10
Internal Architecture ............................................................................................................................. 11
Logical Channel Support .................................................................................................................. 11
Virtual Memory Support .................................................................................................................... 11
Queues ............................................................................................................................................. 12
Scheduling ........................................................................................................................................ 12
Block Diagrams of Possible Systems .................................................................................................12
MPEG Video Compression and Distribution Considerations ........................................................... 13
ATM Subsystem Dataflow .................................................................................................................... 14
Data Flows .......................................................................................................................15
Transmit Path ........................................................................................................................................ 15
Transmit Scheduling Capabilities ....................................................................................................... 16
Receive Path .......................................................................................................................................... 17
Input/Output Definitions .................................................................................................19
PCI Bus Connections ............................................................................................................................ 19
PCI Bus Interface Pin Descriptions .....................................................................................................20
DRAM Memory Bus Interface ............................................................................................................... 21
DRAM Memory Bus Connections ........................................................................................................ 21
DRAM Memory Bus Interface Pin Descriptions ................................................................................. 22