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IBM2520L8767
IBM Processor for ATM Resources
atmrm.chapt05.01
08/27/99
On-chip Checksum and DRAM Test Support (CHKSM)
Page 355 of 553
Initializing Packet/Control Memory
The following list shows the steps to use CHKSM to initialize packet or control memory:
make sure CHKSM is in diagnostic mode, and other mode bits are reset
set the start address by writing the base addr
set up the read/write count with number of bytes to initialize
set up the test pattern register (ripple pattern register) with pattern to use
set up the Control Register to enable test mode, enable checksum entity, and set the memory select bit
correctly based which memory is to be initialized
now busy wait until operation is done (or set up interrupt Enable register and wait for interrupt)
Testing Packet/Control Memory
The following list shows the steps to use CHKSM to test packet or control memory:
first initialize memory with a pattern using above sequence
make sure CHKSM is in diagnostic mode, and other mode bits are reset
set the start address by writing the base addr
set up the read/write count with number of bytes to test (same as initialization value)
the test pattern register (ripple pattern register) already contains the pattern
set up the Control Register to enable test mode, turn on RW bit, enable checksum entity, and set the
memory select bit correctly based which memory is to be initialized
now busy wait until operation is done (or set up interrupt Enable register and wait for interrupt)
When done, check the status register for any errors
Using Ripple Pattern Generation/Checking in Packet/Control Memory
The procedures to use the ripple pattern generation and checking, are the same as using test write/read
modes. The only difference is that the use ripple pattern mode bit must be set and the ripple pattern base
register must be set up.
Running a TCP/IP Checksum in Packet/Control Memory
The following list shows the steps to use CHKSM to generate/verify a TCP/IP checksum:
make sure CHKSM is in diagnostic mode (not enabled)
set the start address by writing the base address
set up the read/write count with number of bytes to run checksum over, and set the upper two bits of the
read/write count register. Writing these upper two bits assumes other mode bits are set correctly (i.e.
memory bank select).
now busy wait until operation is done (or set up interrupt Enable register and wait for interrupt)