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IBM2520L8767
IBM Processor for ATM Resources
Packet Header
Page 36 of 553
atmrm.chapt03.01
08/27/99
Receive Packet Header Structure
struct rx_packhead {
bit16 rx_label;
bit4 reserved;
bit1
bit1
bit1
bit1
bit1
bit1
bit1
bit1
bit1
bit1
bit1
bit1
bit8
bit8
bit16 buffer_length;
bit25 lc_address;
bit6
reserved;
bit1
cell_loss_priority;
bit32 rx_atm_header;
bit32 host_data;
struct rx_packhead {
bit16 rx_label;
bit4 reserved;
bit1
toobig_status;
bit1
memchk_status;
bit1
fabort_status;
bit1
badlen_status;
bit1
badcpi_status;
bit1
badcrc_status;
bit1
timout_status;
bit1
fifopk_status;
bit1
congestion_status;
bit1
route_status;
bit1
error_status;
bit1
done_status;
bit8
AAL5_user_byte;
bit8
buffer_offset;
bit16 buffer_length;
bit25 lc_address;
bit6
reserved;
bit1
cell_loss_priority;
bit32 rx_atm_header;
bit24 host_data;
bit8
AAL5_user_byte2;
toobig_status;
memchk_status;
fabort_status;
badlen_status;
badcpi_status;
badcrc_status;
timout_status;
fifopk_status;
congestion_status;
route_status;
error_status;
done_status;
AAL5_user_byte;
buffer_offset;
bit32 cut_thru_addr;
};
bit32 cut_thru_addr;
};
Transmit and Receive Packet Header Field Descriptions
(Page 1 of 2)
Field Name
Field Description
next_buffer
This field is used by the hardware to chain buffers together on queues. It contains the address of the next buffer
if one exists. For transmit buffers allocated in virtual memory, this field will be written by the hardware with a dis-
tinctive pattern (’zzzzzBAD’x) where zzzzz is the offset of the failure when a write operation was not able to
complete due to a shortage of the real buffers needed to map into the virtual address space. This field can be
checked after all buffer write operations and the appropriate recovery actions taken immediatly, or when a
buffer that has had a write failure is enqueued to CSKED, an event will be generated and the buffer will not be
processed by CSKED. A status bit also exists in the BCACH status register indicating that a write to virtual
memory has failed. With cache performance in mind, this status bit could be checked first, and if it is not set,
there is no need to access the header of the packet.
Note:
This automatic error recovery mechanism results in the restriction that this first four bytes of a transmit
packet must never be written via programmed IO or DMA during preparation for transmission. If this field is writ-
ten by a software or DMA operation, the automatic error detection will not work properly and undesirable results
are likely.
AAL5_user_byte1
This field contains the value to be sent in the user byte in the last cell of an AAL5 packet if INTST is configured
for one user byte.
dma_on_xmit
If this bit is set, a DMA descriptor address placed in the packet header (offset ’C’x) will be queued for execution.
generate_CRC10
If this bit is set, CRC10 will be generated over the cell(s) in this packet.
free_on_xmit
If this bit is set, the buffer will be freed after the transmission completes.
queue_on_xmit
If this bit is set, the buffer will be queued on the transmit complete queue after the transmission completes.