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| 型號(hào)： | IBM25CPC710AB3A100 |
| 廠商： | IBM Microeletronics |
| 英文描述： | IBM Dual Bridge and Memory Controller(IBM雙橋和存儲(chǔ)器控制器（連接帶同步動(dòng)態(tài)RAM存儲(chǔ)器的Power PC 60x總線和兩個(gè)PCI端口）) |
| 中文描述： | IBM的雙橋和內(nèi)存控制器（IBM的雙橋和存儲(chǔ)器控制器（連接帶同步動(dòng)態(tài)RAM的存儲(chǔ)器的Power PC處理器60倍的PCI總線和兩個(gè)端口）） |
| 文件頁(yè)數(shù)： | 204/224頁(yè) |
| 文件大小： | 3278K |
| 代理商： | IBM25CPC710AB3A100 |
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IBM25CPC710AB3A100
IBM Dual Bridge and Memory Controller
Page 192 of 208
dbamc01_ch5.fm.01
July 13, 2000
7. DMA Controller
7.1 Introduction
The DMA Controller controls data transfers between system memory and the PCI buses. Data can be trans-
ferred without DMA control only by gaining master access to a PCI bus. The controller runs with an elemen-
tary block of up to 4 KB. In Extended Mode, automatic chaining is performed during elementary DMA
transfers. Up to 65,000 iterations can be programmed with address increments to transfer up to 256 MB of
data in a single DMA. Address increments are performed after each DMA. An end-of-transfer DMA interrupt is
raised only after multiple chained DMAs are complete.
DMAs are initiated by either a eciwx (read) or ecowx (write) instruction from the processor and ended by an
External Interrupt command. The controller uses an elementary burst of 32 Bytes on the PCI bus to facilitate
interleaved PCI bus operations. The eciwx and ecowx instructions use the processor
’
s internal address trans-
lation logic to present real addresses on the system bus. This eliminates the need for external hardware to
translate virtual addresses and for software to calculate real addresses. Because the DMA is virtual, no soft-
ware overhead is required for pinning system memory that would otherwise be needed if the DMA operated in
real address mode.
Execution of an eciwx or ecowx instruction involves the same sequence as a normal cache inhibited load and
store with a few exceptions. The processor calculates an effective address, translates it, and presents the
resulting real address to the system bus as normal. However, this address bus does not select the slave. The
address is passed to the slave to be used on a subsequent transfer. The slave is selected by a 4-bit Resource
ID (RID) that is placed on the SYS_TBST and SYS_TSIZ[0:2] signals by the processor.
The device is selected for these transactions when the RID on the bus matches Configuration Register bits 8-
11 in the device
’
s System Control Register. The bus transaction is always a single beat regardless of the
SYS_TBST signal setting. While the DMA is occurring, the device monitors the bus for a TLB Sync (resulting
from normal page maintenance by the OS kernel) to terminate the transfer. Software can then restart the
transfer at the faulting address.
The DMA Controller transfers data between system memory and PCI only. It cannot perform memory-to-
memory transfers. DMA operation is transparent to the PCI adapter, which behaves as a PIO slave device.
Although eciwx and ecowx both initiate DMA, the preferred instruction is ecowx because it writes to the
system bus. eciwx is provided to avoid access violation errors on pages marked read-only.
Software ensures proper implementation of the DMA operation, including address alignments and page
boundaries. The device aborts a DMA transfer when any of the following conditions are detected:
TLBSYNC operation detected (internal commands are completed before termination).
Improper DMA transfer setup.
Second DMA transfer initiated when one is already in progress.
The transfer crosses a page boundary.
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