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IBM3206K0424
Preliminary
IBM Processor for Network Resources
pnr25.chapt02.01
August 14, 2000
ATM PHY Bus Interface
Page 59 of 676
1
JTAGTDO
Output
Test Data Output is used to serially shift test data and test instructions out of the
device during TAP operation. (
LSSD test function - PRSRAMABDONE and
PLLLOCK output
)
1
PINTCLK
Output
This is the external test point to measure the jitter effects of the phase-lock loop
circuit. PINTCLK does not serve any LSSD or MFG test function. It does not
need to be on a TEST/NOSCAN location.
1
PDBLCLK
Output
This is the external test point that is double the frequency of the PINTCLK. It is
used to clock ENSTATE state signals at this frequency. PDBLCLK does not
serve any LSSD or MFG test function. It does not need to be on a TEST/NOS-
CAN location.
1
PPLLOUT
Output
This is an observation output only. This makes the output of the PLL observ-
able. This is also the DTR signal when the SELRS232 is active.
1
BIST
n
DI1
Output
Drives the DI input during BIST.
1
DTR
Input or Output
RS232 DTR for the core debugger. (
LSSD test function - TCLKA-AC)
1
CTS
Input
RS232 CTS for the core debugger. (
LSSD test function - LPRA bypass-TI)
1
TXD
Input or Output
RS232 TXD for the core debugger. (
LSSD test function - CLKDIVTCLKB-BC)
1
RXD
Input or Output
RS232 RXD for the core debugger. (
LSSD test function - BSCANTCLKB-BC)
1
RTS
Input or Output
RS232 RTS for the core debugger. (
LSSD test function - BSCANTCLKC-SC)
1
DSR
Input or Output
RS232 DSR for the core debugger. (
LSSD test function - pll testout)
1
IBDINH1
Input
This is the Boundary Scan input for BSINH1.
1
IBDINH2
Input
This is the Boundary Scan input for BSINH2(*).
1
IBDRINH
Input
This is the Boundary Scan input for rinh.
1
LEAKTST
Input
This is the STI driver/receiver leak test input.
2
PLLTUNE(1:0)
Input
These inputs help tune the PLL operation. (
LSSD test function -
SCANOUT(15,14))
1
MPLLRESET
Input
This input is active low and resets the PLL at power up to avoid VCO runaway.
This requires a reset circuit that delays a low-to-high level after power-on-reset
by 150
μ
s. (
LSSD test function - this pin functions as the TESTCT [Test Clock
Tree] input. When not asserted, this chip runs as specified. When asserted, the
clock tree uses this input to control the clokc tree outputs - TI)
1
JTCOMPLY
Input
This input is high for JTAG compliance and low for RISCWatch/BIST-friendly
use. When this pin is high, JTAG boundary scan operations may be used to test
chip I/O operation and card wiring without supplying clocks to the rest of the
chip. Also, when the TAP controller enters the TEST LOGIC RESET state, the
JTAG instruction is IDCODE. When this pin is low, the JTAG boundary scan
logic works only if the other chip clocks are running in a normal functional man-
ner. When the TAP controller enters the TEST LOGIC RESET state, the JTAG
instruction is BYPASS in order to make this more compatible with RISCWatch.
(
LSSD test function - SRAM BIST result output)
Clock, Configuration, and LSSD Pin Descriptions
(Continued)
Quantity
Pin Name
Input/Output
Pin Description