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| 型號(hào)： | IBM3209K3114 |
| 廠商： | IBM Microeletronics |
| 英文描述： | IBM Packet Routing Switch Serial Interface Converter(IBM封裝路線選擇開(kāi)關(guān)串行接口轉(zhuǎn)換器) |
| 中文描述： | IBM的分組路由交換機(jī)串行接口轉(zhuǎn)換器（IBM的封裝路線選擇開(kāi)關(guān)串行接口轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 13/152頁(yè) |
| 文件大?。?/td> | 2390K |
| 代理商： | IBM3209K3114 |
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IBM3209K3114
Advance
IBM Packet Routing Switch Serial Interface Converter
prssi.01
July 12, 2000
Converter Ingress/Egress Data Flow
Page 3 of 142
2. Converter Ingress/Egress Data Flow
The ingress block is the receive path between the protocol engine device (PE) and the rest of the IBM Packet
Routing Switch Serial Interface Converter logic. The egress block is the transmit path between the converter
transmit logic and the PE. This section provides an overview of functions implemented in the converter
ingress and egress data flows. Some functions are duplicated to support two switch planes.
2.1 Ingress Data Flow
2.1.1 Protocol Engine (PE) Ingress Interface
The converter connects to the PE via a 32-bit bus. Ingress data packets are simultaneously routed to PATH X
and to PATH Y. Idle packets are inserted in the word stream when there is no data to transfer and are used to
maintain a synchronous packet operation in the ingress interface. Idle packets are identified by a bit in the
packet qualifier byte.
A Receive Start of Packet (RXSOP) synchronized with the data packet is used to delin-
eate packets.
Combined with the RXPRTY signal issued from the PE, the ingress interface checks the parity coherency on
each incoming RXDATA [31:0]. A specific bit in the configuration table registers can be set so each parity
error issued from the parity checker is reported.
Under the control of the configuration table, RXPRTY_error assertion indicates that the cell that is currently
pushed into the ingress reshuffling buffer will be optionally ignored and will not be sent to the ingress FIFO.
Cells which are pushed into the ingress FIFOs (X/Y RX FIFOs) are always good and can be treated by the
data flow.
2.1.2 Ingress Packet Reshuffling
The ingress logical unit framing block maps incoming data packets into the IBM 28.4 G Packet Routing
Switch (switch) logical units (LUs) by moving the five bytes (the packet qualifier and the bit map fields)
selected from the configuration register into the master LU, which becomes the switch header information
field. The framing block also extracts the IBFC information, discards idle packets, and performs parity
checking on the switch header.
2.1.3 Ingress Receive FIFO
The ingress receive FIFOs provide packet synchronization between the 50 - 125 MHz PE interface and the
110 - 125 MHz switch core interface.
2.1.4 Ingress Data Aligned Serial Link Interface (IDI)
The IDI sends packets continuously. Synchronization packets are sent during the DASL synchronization
sequence. Data or idle packets are sent once data mode is active. On request, through the configuration
table, the LU serializer is filled with a yellow packet and the incoming data packet is buffered while the yellow
packet is sent. When there is no data packet to be transmitted to the switch core, the IDI inserts an idle
packet, computes the inter idle CRC for each LU, and inserts it as the last byte of each LU.
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