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參數(shù)資料
| 型號： | IBM3209K3114 |
| 廠商： | IBM Microeletronics |
| 英文描述： | IBM Packet Routing Switch Serial Interface Converter(IBM封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器) |
| 中文描述： | IBM的分組路由交換機串行接口轉(zhuǎn)換器（IBM的封裝路線選擇開關(guān)串行接口轉(zhuǎn)換器） |
| 文件頁數(shù)： | 146/152頁 |
| 文件大?。?/td> | 2390K |
| 代理商： | IBM3209K3114 |
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IBM3209K3114
IBM Packet Routing Switch Serial Interface Converter
Advance
Appendix A: Data Aligned Serial Link (DASL)
Page 136 of 142
prssi.01
July 12, 2000
No signal register
Sync Status and Sync Hunt register
Sync Packet Transmit register
Signal detect Interrupt in Status register
The Sync Status register reports the status of the input receiver, and the Sync Hunt register forces the input
ports to start the synchronization sequence.
The Sync Packet Transmit register specifies that synchronization packets have to be transmitted in order for
the remote chip input port to synchronize. When not transmitting synchronization packets, the output ports
transmit normal traffic packets: data packets or idle packets.
The following steps must be taken in order to synchronize input ports, either after reset and initialization of the
chip or when the control processor decides to re-synchronize a link due to data errors on the incoming links.
Even if the same steps have to be taken on both the switch port and the IBM Packet Routing Switch Serial
Interface Converter (the converter) chip, they don't have to be synchronous, but the global sequence of oper-
ation must be followed:
1. Disable the switch and converter ports.
2. Enable the switch and converter ports by writing binary '1' Port Enable register.
3. Disable DASL transmission by disabling 'transmit synch enable'.
4. Check for valid connectivity of the receiver to a differential transmitter through the No Signal Register.
This ensures the integrity of the serial links.
5. Enable 'Transmit Sync Packets'.
6. Enable DASL transmission by writing a 1 in 'transmit synch enable'.
7. Write a 1 into the Sync Hunt register for the enabled ports to start synchronization.
8. Poll the Sync Status register to verify completion of synchronization after a Sync Time-Out period. If the
port fails to synchronize, its Sync Status bits will be `0'.
9. When synchronization has been achieved the local processor at each end reports to the control proces-
sor that it is ready for data transfer.
10. Clear any CRC error indication that might have been set up during the synchronization period.
11. Upon reception of both reports the control processor indicates to both ends of the full duplex link (switch
port and converter) to stop transmitting Sync packets. Normal packet transfer (idle or data) on the input
ports can then be initiated.
12. As the link is now in data mode both the switch control and the adapter controller have to poll the CRC
error registers and the No Signal Register to check that the receiver is synchronized and for error free
operation.
This operational sequence is mapped in the following flow chart:
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