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IBM32NPCXX1EPABBE66
IBM Processor for Network Resources
Preliminary
Page xii
pnr261TOC.fm.06
August 14, 2000
3.20.4 RS-232 Transmit Buffer ......................................................................................................491
3.20.5 RS-232 Receive Buffer .......................................................................................................492
3.20.6 RS-232 Baud Rate Register ...............................................................................................492
3.20.7 RS-232 CTS/DSR Glitch Timer Rate ..................................................................................493
3.20.8 RS-232 Reset Register .......................................................................................................493
3.20.9 RS-232 Error Forcing Register ...........................................................................................494
3.21 PowerPC On-Chip Memory (PPOCM) Entity ............................................................................495
3.21.1 DMA Controller ...................................................................................................................495
3.21.2 PPOCM Control Register ....................................................................................................495
3.21.3 PPOCM Status Register .....................................................................................................496
3.21.4 PPOCM Interrupt Enable Register ......................................................................................497
3.21.5 PPOCM DMA Off-Chip Effective Address Register ............................................................497
3.21.6 PPOCM DMA On-Chip Effective Address Register ............................................................498
3.21.7 PPOCM DMA Length Register ...........................................................................................498
3.21.8 PPOCM DMA Timeout Timer Register ...............................................................................499
3.22 JTAG Interface Logic (CJTAG) ..................................................................................................501
3.22.1 Scanning .............................................................................................................................501
3.22.2 Instruction Format ...............................................................................................................502
3.22.3 Instructions ..........................................................................................................................503
3.22.3.1 IDCODE .......................................................................................................................503
3.22.3.2 SAMPLE/PRELOAD ....................................................................................................503
3.22.3.3 EXTEST .......................................................................................................................503
3.22.3.4 BYPASS ......................................................................................................................503
3.22.3.5 RUNBIST .....................................................................................................................503
3.22.3.6 BIST_RESULTS ..........................................................................................................504
3.22.3.7 COMPATIBLE_MODE .................................................................................................504
3.22.3.8 COMPLIANT_MODE ...................................................................................................504
3.22.3.9 STOP ...........................................................................................................................504
3.22.3.10 SCAN .........................................................................................................................504
3.22.3.11 SCAN_IN ...................................................................................................................504
3.22.3.12 SCAN_OUT ...............................................................................................................505
3.22.3.13 Private_RW1 .............................................................................................................505
3.22.3.14 Private_RW2 .............................................................................................................505
3.22.3.15 Private_RW3 .............................................................................................................505
3.23 Sonet Framer Core (FRAMR Chiplet Address Mapping) ........................................................507
3.23.1 Description of GPPINT ........................................................................................................507
3.23.1.1 Overview ......................................................................................................................507
3.23.1.2 Reset Register .............................................................................................................507
3.23.1.3 Interrupt Registers .......................................................................................................507
3.23.1.4 Handshaking Error Registers ......................................................................................507
3.23.1.5 Clock Monitor Status Registers ...................................................................................508
3.23.1.6 Local GPPINT Configuration Registers .......................................................................508
3.23.1.7 Global Static Configuration Registers ..........................................................................508
3.23.1.8 Status Registers ..........................................................................................................508
3.23.2 Description of GPPHandler .................................................................................................509
3.23.2.1 Overview ......................................................................................................................509
3.23.2.2 Counter Registers ........................................................................................................509
3.23.2.3 Reset Registers ...........................................................................................................509
3.23.2.4 Command Registers ....................................................................................................509
3.23.2.5 Event Latch Registers .................................................................................................510
3.23.2.6 Interrupt Registers .......................................................................................................510