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IBM32NPCXX1EPABBE66
IBM Processor for Network Resources
Preliminary
NPBUS Interface
Page 22 of 706
pnr261_2io.fm.06
August 14, 2000
Table 8: NPBUS Signal Descriptions
Signal Name
Quantity
Type
Function
Description
PB0PHY1
1
Output
Select PHY 1
When low, indicates that the PNR has selected PHY 1 to write to
control registers inside PHY 1 or to read either the control or status
registers.
PB0PHY2
1
Output
Select PHY 2
When low, indicates that the PNR has selected PHY 2 to write to
control registers inside PHY 2 or to read either the control or status
registers. See
3.16.1: NPBUS Control Register
on page 387 for
more details.
If configured, this pin can also be odd parity across the eight-bit
wide bidirectional data bus. It can also be configured as
MPMDSEL: this control pin, under register bit control, can drive a
logical value out. The intention is to select between the different
PMD types on the 155 Mb/s copper card (UTP verses STP). If it is
in cascade mode, this bit functions as PIDSELO (+idsel out), which
the primary PNR will drive to the secondary PNR when trying to
update configuration space via configuration cycles. This multi-
plexed pin also carries the PBDATAP signal.
ENSTATE
(63-0)
64
Output
When programmed, drives out the real-time state-of-entity state
machines, counters, etc. for debug purposes. The (47-32) bits of
this bus are also PBADDR(15-0), which are the address lines for
the external parallel EPROM or PHY. Additionally, bits 47-40 can
be used as bi-directional data bus bits to extend the PBDATA bus
by providing bits 15-8 of this bus. This allows operation with PHY
parts that have a fixed 16-bit data but limits the addressing to this
PHY to only eight address bits. (
LSSD test function - scanout(13 to
0) -SO -BDY
)
PB0EPRM
1
Output
EPROM Select
When low, indicates that the PNR has selected the external
EPROM to read from. After reset, the PNR will start accessing the
optional on-card ROM/EPROM and do the chip initialization func-
tion if it does not find a serial EPROM attached.
PBALE1
1
Output
Address Latch Enable
1
When high, indicates that the PNR has generated an address on
the PBDATA bus and should be latched by either a PHY that sup-
ports this muxing or an external octal latch TTL part. For an exter-
nal EPROM, it will also latch bits 7-0 of the address for an external
EPROM access.
PBALE2
1
Output
Address Latch Enable
2
When high, indicates that the PNR has generated an address on
the PBDATA bus and should be latched by an external octal latch
TTL part that holds bits 15-8 of the address for an external EPROM
or PHY access.
PBADDR16
1
Output
Address Send 16
Supplies address 16 to an external EPROM. The pin will also func-
tion as PBALE3, an address latch enable, that indicates that the
PNR has generated an address on the PBDATA bus and should be
latched by an external octal latch TTL part that holds bits 23-16 of
the address for an external EPROM access. The mechanism used
to set this mode is to put a pull-down resistor on this pin. At reset
time, it will be detected and set this bit in PBALE3 mode. Otherwise
it will be in PBADDR16 mode.
PBADDR17
1
Output
Address Send 17
Supplies address 17 to an external EPROM.
PBSCLK
1
Output
Clock for the I
2
C serial
EPROM accesses
S/T/S = a sustained tri-state pin owned and driven by one and only one agent at a time. The agent that drives the S/T/S pin low must
drive it high for at least one clock before letting it float. A new agent cannot start driving a S/T/S signal any sooner that one clock after
the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it and must be provided by the
central resource.