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參數(shù)資料
| 型號： | IBM39MPEGCS24PFA16C |
| 廠商： | IBM Microeletronics |
| 英文描述： | High Performance Audio/Video Decoder(高性能音頻/視頻譯碼器) |
| 中文描述： | 高性能音頻/視頻解碼器（高性能音頻/視頻譯碼器） |
| 文件頁數(shù)： | 11/22頁 |
| 文件大小： | 278K |
| 代理商： | IBM39MPEGCS24PFA16C |
IBM39MPEGCS24PFA16C
IBM39MPEGCS24DPFA16C
High Performance Audio/Video Decoder
mpegcs24ds.00
12/10/99 Summary Datasheet
Pin and Signal Information
Page 11 of 21
Pin and Signal Information
In the following tables the use of overbars, for example RESET, designates signals that are active low. All sig-
nals with no overbar are assumed to be active high.
Pin Descriptions
Signal Name
Description
Pin Type
27 MHz CLK
27 MHz Clock
Input
64MBIT_A11
64MBIT_A11
Output
64MBIT_BA1
64MBIT_BA1
Output
AUD 1 CLK
Audio 1 Clock
Output
AUD1 DAC CLK
Audio 1 DAC Clock
Output
AUD1 DATA(n)
Audio 1 Data Out(n)
Output
AUD1 DEEMPHASIS(n)
Audio 1 Deemphasis(n)
Output
AUD1 DSURMOD(n)
Audio 1 Dolby Sur Mode(n)
Output
AUD1 L/R
Audio 1 Left / Right
Output
AUD1 REQ
Audio 1 Data Request
Output
AUD1 SPDIF
Audio1 S/PDIF
Output
AUD1 STROBE
Audio 1 Compressed Data Strobe
Input
AUD2 CLK
Audio 2 Clock
Output
AUD2 DAC CLK
Audio 2 DAC Clock
Output
AUD2 DATA(n)
Audio 2 Data Out(n)
Output
AUD2 DEEMPHASIS(n)
Audio 2 Deemphasis(n)
Output
AUD2 DSURMOD(n)
Audio 2 Dolby Sur Mode(n)
Output
AUD2 L/R
Audio 2 Left/Right
Output
AUD2 REQ
Audio 2 Data Request
Output
AUD2 SPDIF
Audio 2 S/PDIF
Output
AUD2 STROBE
Audio 2 Compressed Data Strobe
Input
BA0
BA0
Output
CAS
Column Address Select
Output
CD21 MODE
CD21 Mode
Input
CKE
SDRAM Clock Enable
Output
CLK
SDRAM Clock
Output
CREF
Video Clock Reference
Output
CS
Chip Select
Input
CS0
SDRAM Chip Select 0
Output
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