參數(shù)資料
型號(hào)： IBM42M10SNYAA20
廠商： IBM Microeletronics
英文描述： 1063 MB/S Gigabit Link Module(1063 MB/S 吉位連接模塊（高性能集成光纖收發(fā)器）)
中文描述： 1063 MB / s的千兆連接模塊（1063 MB /秒吉位連接模塊（高性能集成光纖收發(fā)器））
文件頁(yè)數(shù)： 8/26頁(yè)
文件大?。?/td> 436K
代理商： IBM42M10SNYAA20
IBM42M10SNYAA20
IBM42M10LNYAA10
1063Mb/s Gigabit Link Module - No OFC
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 26
GLM1063N.02
11/10/99
Input Signal Definitions
Levels for the signals described in this section are listed in Digital Inputs on page 15.
Transmit Byte Clock (TBC)
The system logic provides a single-phase Transmit Byte Clock for transmission operations. The relationship
between the Transmit Data and the Transmit Byte Clock is shown in the Transmit Timing diagram below.
Transmit Data (Tx[00:19])
Two 10-bit pre-encoded data bytes from the system logic are presented to the GLM for serialization. Byte 0,
comprised of bits Tx00 through Tx09, is launched first. Byte 1, comprised of Tx10 through Tx19, is launched
last. The Transmit Timing diagram below shows the Setup and Hold Times for the Transmit Data.
Lock to Reference (Lck_Ref)
This active low signal causes the deserializer PLL to acquire frequency lock on the Transmit Byte Clock
(TBC). The Lock to Reference Timing diagram shows the required Lock to Reference time and the wait time
for valid data.
The Lock to Reference line is used in the operation of the receiver PLL. When the incoming data stream is
absent (e.g. when the companion GLM is in wrap mode), the receiver PLL will drift to a minimum or maximum
frequency (27 to 106 MHz) which is far from the nominal operating point. If the incoming data is turned back
on, the PLL will attempt to readjust and may lock onto either the incoming data rate
or to one of its harmonics
.
To guarantee that the PLL locks on to the fundamental frequency of the incoming data, the Lock to Reference
line is driven low, forcing the PLL to lock onto the Transmit Byte Clock supplied by the system (which is
extremely close to the frequency of the incoming data). It takes a maximum of 500
ν
s for the PLL to lock onto
to the Transmit Byte Clock reference. Thereafter, the Lock to Reference line is driven high by the system and
the incoming data stream is directed into the receiver PLL. The receiver PLL will achieve phase and fre-
quency lock of the incoming data within 2500 bit times (2.4
ν
s).
The designer needs to be careful in choosing when the logic exercises the Lock to Reference signal. Since
the receiving system is not generally in control of the incoming signal, it must make some savvy decisions
about when PLL synchronization is lost.
Transmit and Lock to Reference Timings
ν
s)
>500
ν
s
!
Data valid after receipt of first K28.5
<2500 bit (2.4
Rx[00:19]
Lck_Ref
Transmit
Byte Clock
Tx[00:19]
!
Data must be valid
18.8ns
>3.3ns
>2.0ns
Note:
positive edge of the Transmit Byte Clock.
All critical timings are referenced to the
Transmit Timing
Lock to Reference Timing
In most instances, the minimum required Lock To Reference
time is 120ms (rather than 500ms).
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