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參數(shù)資料
| 型號： | IBMB6M32734HGA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x72 One Bank Registered DDR SDRAM Module(32M x 72 1組寄存同步雙數(shù)據(jù)速率動態(tài)RAM模塊) |
| 中文描述： | 32M的x72第一銀行注冊DDR SDRAM內(nèi)存模塊（32M × 72配置一組寄存同步雙數(shù)據(jù)速率動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 13/23頁 |
| 文件大?。?/td> | 421K |
| 代理商： | IBMB6M32734HGA |
IBMB6M32734HGA
Preliminary
32Mx72 One Bank Registered DDR SDRAM Module
19L7358.H02502A
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 23
t
RAS
Active to Precharge command
50
120,000
ns
1, 2, 3, 4
t
RC
Active to Active/Auto-refresh command period
70
ns
1, 2, 3, 4
t
RFC
Auto-refresh to Active/Auto-refresh command
period
80
ns
1, 2, 3, 4
t
RCD
Active to Read or Write delay
20
ns
1, 2, 3, 4
t
RAP
Active to Read Command with Autoprecharge
20
ns
1, 2, 3, 4
t
RP
Precharge command period
20
ns
1, 2, 3, 4
t
RRD
Active bank A to Active bank B command
15
ns
1, 2, 3, 4
t
WR
Write recovery time
15
ns
1, 2, 3, 4
t
DAL
Auto precharge write recovery + precharge
time
(t
WR
÷
t
CK
) +
(t
RP
÷
t
CK
)
t
CK
1, 2, 3, 4, 16
t
WTR
Internal write to read command delay
1
t
CK
1, 2, 3, 4
t
XSNR
Exit self-refresh to non-read command
80
ns
1, 2, 3, 4
t
XSRD
Exit self-refresh to read command
200
t
CK
1, 2, 3, 4
t
REFI
Average Periodic Refresh Interval
7.8
μ
s
1, 2, 3, 4, 8
t
QCS
QFC setup time on Read
0.9
1.1
t
CK
1, 2, 3, 4, 15
t
QCH
QFC hold time on Read
0.4
0.6
t
CK
1, 2, 3, 4, 15
t
QCSW
Delay from CK edge of write command to QFC
low on write
4.0
ns
1, 2, 3, 4, 9, 15
t
QCHW
QFC hold time on write
1.25
2.0
ns
1, 2, 3, 4, 10, 15
Electrical Characteristics and AC Timing - Absolute Specifications
(0
°
C
≤
T
A
≤
70
°
C
;
V
DDQ
= 2.5V
±
0.2V; V
DD
= 2.5V
±
0.2V, See AC Characteristics) (Part 2 of 2)
Symbol
Parameter
PC 1600
Unit
Notes
Min
Max
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