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| 型號： | IBMB6M32734HGA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x72 One Bank Registered DDR SDRAM Module(32M x 72 1組寄存同步雙數(shù)據(jù)速率動態(tài)RAM模塊) |
| 中文描述： | 32M的x72第一銀行注冊DDR SDRAM內(nèi)存模塊（32M × 72配置一組寄存同步雙數(shù)據(jù)速率動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 15/23頁 |
| 文件大?。?/td> | 421K |
| 代理商： | IBMB6M32734HGA |
IBMB6M32734HGA
Preliminary
32Mx72 One Bank Registered DDR SDRAM Module
19L7358.H02502A
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 23
17. An input setup and hold time derating table is used to increase t
IS
and t
IH
in the case where the input
slew rate is below 0.5 V/ns.
18. An input setup and hold time derating table is used to increase t
DS
and t
DH
in the case where the I/O
slew rate is below 0.5 V/ns.
19. An I/O Delta Rise, Fall Derating table is used to increase t
DS
and t
DH
in the case where DQ, DM, and
DQS slew rates differ.
Input Slew Rate
t
IS
t
IH
Unit
Note
0.5 V/ns
0
0
ps
1, 2
0.4 V/ns
+ 50
0
ps
1, 2
0.3 V/ns
+ 100
0
ps
1, 2
1. Input slew rate is based on the lesser of the slew rates determined by either V
IH (AC)
to V
IL (AC)
or V
IH (DC)
to V
IL (DC)
, similarly for
rising transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each
device.
Input Slew Rate
t
DS
t
DH
Unit
Note
0.5 V/ns
0
0
ps
1, 2
0.4 V/ns
+ 75
+ 75
ps
1, 2
0.3 V/ns
+ 150
+ 150
ps
1, 2
1. I/O slew rate is based on the lesser of the slew rates determined by either V
IH (AC)
to V
IL (AC)
or V
IH (DC)
to V
IL (DC)
, similarly for
rising transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each
device.
Delta Rise and Fall Rate
t
DS
t
DH
Unit
Note
0.0 ns/V
0
0
ps
1, 2,
3, 4
0.25 ns/V
+ 50
+ 50
ps
1, 2,
3, 4
0.5 ns/V
+ 100
+ 100
ps
1, 2,
3, 4
1. Input slew rate is based on the lesser of the slew rates determined by either V
IH (AC)
to V
IL (AC)
or V
IH (DC)
to V
IL (DC)
, similarly for
rising transitions.
2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns
Delta rise, fall = (1/0.5) - (1/0.4) [ns/V]
= -0.5 ns/V
Using the table above, this would result in an increase in t
DS
and t
DH
of 100 ps.
4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each
device.
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