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參數(shù)資料
| 型號： | IBMB6M32734HGA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x72 One Bank Registered DDR SDRAM Module(32M x 72 1組寄存同步雙數(shù)據(jù)速率動態(tài)RAM模塊) |
| 中文描述： | 32M的x72第一銀行注冊DDR SDRAM內(nèi)存模塊（32M × 72配置一組寄存同步雙數(shù)據(jù)速率動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 6/23頁 |
| 文件大?。?/td> | 421K |
| 代理商： | IBMB6M32734HGA |
IBMB6M32734HGA
32Mx72 One Bank Registered DDR SDRAM Module
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 23
19L7358.H02502A
1/01
:
Serial Presence Detect
(Part 1 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
80
08
07
0D
0A
01
4800
04
Notes
0
1
2
3
4
5
Number of Serial PD Bytes Written during Production
Total number of bytes in Serial PD Device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of Physical Banks on DIMM
Data Width of Assembly
Voltage Interface Level of this Assembly
SDRAM Device Cycle Time at Maximum CL
(CLX = 2.5)
SDRAM Device Access Time from Clock at CL=2.5
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Device Width
Error Checking SDRAM Device Width
SDRAM Device Attributes: Minimum Clock Delay,
Random Column Access
SDRAM Device Attributes: Burst Lengths Supported
SDRAM Device Attributes: Number of Device Banks
SDRAM Device Attributes: CAS Latency
SDRAM Device Attributes: CS Latency
SDRAM Device Attributes: WE Latency
128
256
SDRAM DDR
13
10
1
x72
SSTL 2.5V
6-7
8
9
8.0ns
80
1
10
11
12
13
14
0.8ns
ECC
7.8
μ
s/SR
x8
x8
80
02
82
08
08
15
1 Clock
01
16
17
18
19
20
2, 4, 8
4
2, 2.5
0
1
0E
04
0C
01
02
21
SDRAM Module Attributes
Registered with PLL,
Differential clock
V
DD
±
0.2V
10.0ns
26
22
SDRAM Device Attributes: General
80
23
Minimum Clock Cycle at CLX-0.5 (CL = 2)
Maximum Data Access Time (t
AC
) from Clock at CLX-0.5
(CL = 2)
Minimum Clock Cycle Time at CLX-1 (CL = 1.5)
Maximum Data Access Time (t
AC
) from Clock at CLX-1
(CL = 1.5)
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active Delay (t
RRD
)
Minimum RAS to CAS Delay (t
RCD
)
Minimum Active to Precharge Time (t
RAS
)
Module Bank Density - 32Mx72
A0
1
24
±
0.8ns
80
25
N/A
00
26
N/A
00
27
20.0ns
50
28
15.0ns
3C
29
20.0ns
50
30
31
50.0ns
256MB
32
40
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock
cycles] + 1 = DIMM CAS latency).
2. cc = Checksum Data byte, 00-FF (Hex).
3. “R” = Alphanumeric revision code, A-Z, 0-9.
4. rr = ASCII coded revision code byte “R”.
5. ww = Binary coded decimal week code, 01-52 (Decimal)
→
01-34 (Hex).
6. yy = Binary coded decimal year code, 00-99 (Decimal)
→
00-63 (Hex).
7. ss = Serial number data byte, 00-FF (Hex).
8. Setup and hold values assume a 1 Volt/ns slew rate.
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