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參數(shù)資料
| 型號： | IBMB6M32734HGA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x72 One Bank Registered DDR SDRAM Module(32M x 72 1組寄存同步雙數(shù)據(jù)速率動態(tài)RAM模塊) |
| 中文描述： | 32M的x72第一銀行注冊DDR SDRAM內(nèi)存模塊（32M × 72配置一組寄存同步雙數(shù)據(jù)速率動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 7/23頁 |
| 文件大?。?/td> | 421K |
| 代理商： | IBMB6M32734HGA |
IBMB6M32734HGA
Preliminary
32Mx72 One Bank Registered DDR SDRAM Module
19L7358.H02502A
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 23
32
33
34
35
Address and Command Setup Time before Clock
Address and Command Hold Time after Clock
Data/Data Mask Input Setup Time before Clock
Data/Data Mask Input Hold Time after Clock
Reserved
SPD Revision
Checksum for Bytes 0 - 62
Manufacturers’ JEDEC ID Code
Module Manufacturing Location
1.1ns
1.1ns
0.6ns
0.6ns
Undefined
0
Checksum Data
IBM
B0
B0
60
60
00
00
cc
8
36-61
62
63
64-71
72
2
A400000000000000
xx
73-90
Module Part Number
ASCII ‘B6M32734HGA
-8NT’
“R” plus ASCII blank
Year/Week Code
Serial Number
Undefined
Undefined
42364D3332373334484741
2D384E54202020
rr20
yyww
ssssssss
00
00
3, 4
91-92
93-94
95-98
99-127
128-255 Open for Customer Use
Module Revision Code
Module Manufacturing Date
Module Serial Number
Reserved
4
5, 6
7
Serial Presence Detect
(Part 2 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
Notes
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock
cycles] + 1 = DIMM CAS latency).
2. cc = Checksum Data byte, 00-FF (Hex).
3. “R” = Alphanumeric revision code, A-Z, 0-9.
4. rr = ASCII coded revision code byte “R”.
5. ww = Binary coded decimal week code, 01-52 (Decimal)
→
01-34 (Hex).
6. yy = Binary coded decimal year code, 00-99 (Decimal)
→
00-63 (Hex).
7. ss = Serial number data byte, 00-FF (Hex).
8. Setup and hold values assume a 1 Volt/ns slew rate.
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