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參數(shù)資料
| 型號： | IBMN312164CT3 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 128Mb(8Mbit x 4 I/O x 4 Bank) Synchronous DRAM(128M位(8M位 x 4 I/O x 4 組)同步動態(tài)RAM) |
| 中文描述： | 128Mb的（8Mbit × 4的I / O × 4行）同步DRAM（128兆位（800萬位× 4的I / O × 4組）同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 20/66頁 |
| 文件大?。?/td> | 1696K |
| 代理商： | IBMN312164CT3 |
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IBMN312164CT3
IBMN312404CT3
128Mb Synchronous DRAM - Die Revision B
IBMN312804CT3
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 20 of 66
06K7582.H03335A
10/00
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank
undergoing auto-precharge cannot be reactivated until t
DAL
, Data-in to Active delay, is satisfied.
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command
to the same bank. It can be interrupted by a Read or Write Command to a different bank, however. The inter-
rupting command will terminate the write. The bank undergoing auto-precharge can not be reactivated until
t
DAL
is satisfied.
Burst Write with Auto-Precharge
Burst Write with Auto-Precharge Interrupted by Write
DIN A
0
COMMAND
NOP
NOP
NOP
NOP
Auto-Precharge
DIN A
1
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
*
DIN A
0
DIN A
1
t
CK2
,
DQs
CAS latency = 2
t
CK3
,
DQs
CAS latency = 3
NOP
NOP
NOP
*
Bank can be reactivated at completion of t
DAL
.
t
DAL
is a function of clock cycle time and speed sort.
t
DAL
t
DAL
*
(Burst Length = 2, CAS Latency = 2, 3)
See the Clock Frequency and Latency table.
DIN A
0
COMMAND
NOP
NOP
NOP
*
Auto-Precharge
DIN A
1
t
DAL
CK
T0
T1
T2
T3
T4
T5
NOP
t
CK3,
DQs
CAS latency = 3
WRITE B
DIN B
0
DIN B
1
DIN B
2
DIN B
3
T6
T7
T8
NOP
NOP
NOP
*
Bank can be reactivated at completion of t
DAL
.
t
DAL
is a function of clock cycle time and speed sort.
(Burst Length = 4, CAS Latency = 3)
See the Clock Frequency and Latency table.
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