參數(shù)資料
型號(hào)： IBMN312164CT3
廠商： IBM Microeletronics
英文描述： 128Mb(8Mbit x 4 I/O x 4 Bank) Synchronous DRAM(128M位(8M位 x 4 I/O x 4 組)同步動(dòng)態(tài)RAM)
中文描述： 128Mb的（8Mbit × 4的I / O × 4行）同步DRAM（128兆位（800萬(wàn)位× 4的I / O × 4組）同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 25/66頁(yè)
文件大?。?/td> 1696K
代理商： IBMN312164CT3
IBMN312164CT3
IBMN312804CT3
IBMN312404CT3
Preliminary
128Mb Synchronous DRAM - Die Revision B
06K7582.H03335A
10/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 25 of 66
Automatic Refresh Command (CAS before RAS Refresh)
When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters
the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of
the Precharge time (t
RP
) before the Auto Refresh Command (CBR) can be applied. For a stacked device,
both decks may be refreshed at the same time using Automatic Refresh Mode. An address counter, internal
to the device provides the address during the refresh cycle. No control of the external address pins is
required once this cycle has started.
When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay
between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh
Command must be greater than or equal to the Refresh cycle time (t
RFC
).
Self Refresh Command
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command
is defined by having CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks
must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held
low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the
external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Oper-
ation to save power. The user may halt the external clock while the device is in Self Refresh mode, however,
the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the
device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the
device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the
RAS cycle time (t
RC
) plus the Self Refresh exit time (t
SREX
). When using Self Refresh, both decks of a
stacked device may be refreshed at the same time.
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PDF描述
IBMN325404CT3 256Mb（4Mbit x 16 I/O x 4 Bank） Synchronous DRAM(256M位（4M位 x 16 I/O x 4 組）同步動(dòng)態(tài)RAM)
IBMN325804CT3 256Mb（8Mbit x 8 I/O x 4 Bank） Synchronous DRAM(256M位（8M位 x 8 I/O x 4 組）同步動(dòng)態(tài)RAM)
IBMN325164CT3 256Mb（16Mbit x 4 I/O x 4 Bank） Synchronous DRAM(256M位（16M位 x 4 I/O x 4 組）同步動(dòng)態(tài)RAM)
IBMN612404GT3B 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動(dòng)態(tài)RAM（采用雙數(shù)據(jù)速率結(jié)構(gòu)）)
IBMN612804GT3B 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動(dòng)態(tài)RAM（采用雙數(shù)據(jù)速率結(jié)構(gòu)）)
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