- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379206 > IBMN312164CT3 (IBM Microeletronics) 128Mb(8Mbit x 4 I/O x 4 Bank) Synchronous DRAM(128M位(8M位 x 4 I/O x 4 組)同步動(dòng)態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號(hào)： | IBMN312164CT3 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 128Mb(8Mbit x 4 I/O x 4 Bank) Synchronous DRAM(128M位(8M位 x 4 I/O x 4 組)同步動(dòng)態(tài)RAM) |
| 中文描述： | 128Mb的（8Mbit × 4的I / O × 4行）同步DRAM（128兆位（800萬位× 4的I / O × 4組）同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 30/66頁 |
| 文件大?。?/td> | 1696K |
| 代理商： | IBMN312164CT3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
IBMN312164CT3
IBMN312404CT3
128Mb Synchronous DRAM - Die Revision B
IBMN312804CT3
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 30 of 66
06K7582.H03335A
10/00
Clock Enable (CKE) Truth Table
Current State
CKE
Command
Action
Notes
Previous
Cycle
Current
Cycle
CS
RAS
CAS
WE
BS0,
BS1
A11 - A0
Self Refresh
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
Exit Self Refresh with Device Deselect
2
L
H
L
H
H
H
X
X
Exit Self Refresh with No Operation
2
L
H
L
H
H
L
X
X
ILLEGAL
2
L
H
L
H
L
X
X
X
ILLEGAL
2
L
H
L
L
X
X
X
X
ILLEGAL
2
L
L
X
X
X
X
X
X
Maintain Self Refresh
Power Down
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
Power Down mode exit, all banks idle
2
L
H
L
X
X
X
X
X
ILLEGAL
2
L
L
X
X
X
X
X
X
Maintain Power Down Mode
All Banks Idle
H
H
H
X
X
X
Refer to the Idle State section of the
Current State Truth Table
3
H
H
L
H
X
X
3
H
H
L
L
H
X
3
H
H
L
L
L
H
X
X
CBR Refresh
H
H
L
L
L
L
OP Code
Mode Register Set
4
H
L
H
X
X
X
Refer to the Idle State section of the
Current State Truth Table
3
H
L
L
H
X
X
3
H
L
L
L
H
X
3
H
L
L
L
L
H
X
X
Entry Self Refresh
4
H
L
L
L
L
L
OP Code
Mode Register Set
L
X
X
X
X
X
X
X
Power Down
4
Any State
other than
listed above
H
H
X
X
X
X
X
X
Refer to operations in the Current
State Truth Table
H
L
X
X
X
X
X
X
Begin Clock Suspend next cycle
5
L
H
X
X
X
X
X
X
Exit Clock Suspend next cycle
L
L
X
X
X
X
X
X
Maintain Clock Suspend
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for
CKE (t
CES
) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on
the first rising clock after CKE goes high (see page 26).
3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more
information.
4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle
state.
5. Must be a legal command as defined in the Current State Truth Table.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBMN325404CT3 | 256Mb（4Mbit x 16 I/O x 4 Bank） Synchronous DRAM(256M位（4M位 x 16 I/O x 4 組）同步動(dòng)態(tài)RAM) |
| IBMN325804CT3 | 256Mb（8Mbit x 8 I/O x 4 Bank） Synchronous DRAM(256M位（8M位 x 8 I/O x 4 組）同步動(dòng)態(tài)RAM) |
| IBMN325164CT3 | 256Mb（16Mbit x 4 I/O x 4 Bank） Synchronous DRAM(256M位（16M位 x 4 I/O x 4 組）同步動(dòng)態(tài)RAM) |
| IBMN612404GT3B | 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動(dòng)態(tài)RAM（采用雙數(shù)據(jù)速率結(jié)構(gòu)）) |
| IBMN612804GT3B | 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動(dòng)態(tài)RAM（采用雙數(shù)據(jù)速率結(jié)構(gòu)）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBMN364164CT3C360 | 制造商:IBM 功能描述:* |
| IBMPPC403GAJC33C1 | 制造商:IBM 功能描述: |
| IBMPPC750CLGEQ4023 | 制造商:IBM 功能描述:MPU 750CL RISC 32BIT 90NM 400MHZ 1.15V/1.8V 278FCBGA - Trays |
| IBMPPC750CLGEQ5023 | 制造商:IBM Microelectronics 功能描述:MPU 750CL RISC 32BIT 90NM 500MHZ 1.15V/1.8V 278FCBGA - Trays |
| IBMPPC750CLGEQA033 | 制造商:IBM 功能描述:MPU 750CL RISC 32BIT 90NM 1GHZ 1.15V/1.8V 278FCBGA - Trays 制造商:IBM 功能描述:IBMIBMPPC750CLGEQA033 CPU PPC 750CL 1GHZ |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。